Table of Contents
Advertisement
www.ti.com
12.2.3.12 3- or 4-Pin Mode
External SPI bus interface can be configured to use a restricted set of pin using the bit field
MCSPI_MODULCTRL[1] PIN34 and depending on targeted application:
•
If MCSPI_MODULECTRL[34] is cleared to 0 (default value) the controller is in 4-pin mode using the
SPI pins CLKSPI, SOMI, SIMO and chip enable CS.
•
If MCSPI_MODULECTRL[34] is set to 1 the controller is in 3-pin mode using the SPI pins CLKSPI,
SOMI and SIMO.
In this mode it is mandatory to put the controller in single channel master mode
(MCSPI_MODULECTRL[SINGLE] asserted) and to connect only one SPI device on the bus.
Local
Host
System
Clock
Unit
System
Interrupt
System
DMA
*CLK: Functional Reference Clock
In 3-pin mode all options related to chip select management are useless:
•
MCSPI_CHxCONF[EPOL]
•
MCSPI_CHxCONF[TCS0]
•
MCSPI_CHxCONF[FORCE]
The chip select pin SPIEN is forced to '0' in this mode.
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Preliminary
Figure 12-21. 3-Pin Mode System Overview
McSPI
(Master/Slave)
CLK*
SPI Interface
WAKE_REQ
Reference Clock
DMA_TX_REQ
© 2011, Texas Instruments Incorporated
External SPI Compliant Devices
(Single Master or Slave)
SPICLK
(Touch Screen,
SPIDAT[0]
LCD, Audio
SPIDAT[1]
Codec, etc.)
SPIEN[3:0]
ASIC
Multichannel Serial Port Interface (McSPI)
Architecture
1239
Advertisement
Table of Contents
