Table of Contents
Advertisement
Reset Management
14.5.3 Global Power-On (Cold) Reset
The PRCM is required internally to generate the global power-on reset used by the domain Reset
Managers from three cold reset sources: SYS_PWRN_RST, ICEPICK_POR_RST,
GLOBAL_COLD_SW_RST.
Source SYS_PWRN_RST is received over a dedicated device input pin, typically driven by the same
power IC that supplies device power and 27MHz clock. This is the normal system POR.
The internal emulation module, ICE-Pick, generates ICEPICK_POR_RST. This reset is used in
emulation mode only.The PRCM is required to provide an output port, ACT_LIKE_SECURE, which is
asynchronously set to a logic high upon ICEPICK_POR_RST assertion. This state is maintained until a
normal system POR occurs.
Source GLOBAL_COLD_SW_RST is a PRM internally generated one. Activation is triggered upon
setting PRM memory-mapped register bit, PRM_RSTCTRL.GLOBAL_COLD_SW_RST. This bit is
self-clearing, i.e., it is automatically cleared by the hardware.
All the reset driven by the PRCM are asserted when any one of global power on reset sources above
are active. The PRCM must stall the release of the global power-on reset until after de-assertion of all
cold reset sources and until after receiving indication that the voltage domains, have all ramped to their
operating levels and until after receiving an indication that the system clock is running and is stable.
The PRCM implements a counter after all of these indications have occurred to provide a delay before
releasing internal global power on reset signals. This requires use of a PM FW Reset Manager. The
"always-on" 27 MHz clock must run the RM's stall-period timer. The max count is provided by PRM
register RM_RSTTIME.RSTIME1 bit-field. During device power-up, this mechanism enforces the
system requirement of a running 27 MHz clock.
14.5.3.1 Power-On Reset Sequence
The following sequence describes the main chronological steps during the power-on reset sequence of
the device.
•
The system settings are done (all the voltages are ramped-up, 27 MHz clock is stable, power
domains are ramped up) and now SYS_PWRN_RST is de-asserted and the PRCM proceeds with
the device power-up sequence.
•
Following the de-assertion of this power on reset signal, the PRCM starts the power on reset
sequence.
•
"SYS_WARM_OUT_RESET" will be de-asserted by PRCM.
•
The DPLLs are released from reset.
•
The MPU is released from reset provided the MPU clock is running.
•
Once "MPU_RST_DONE" is asserted by MPU, all other domain resets are released provided the
domain clocks are running.
•
All the software controlled resets, will either remain asserted/De-asserted as per the default MMR
bit.
14.5.4 Global Warm Reset
The PRCM is required to generate the global reset used by the domain Reset Managers from following
warm reset input sources: SYS_WARM_IN_RST, SECURE_WD_RST, MPU_WD_RST,
MPU_SECURITY_VIOL_RST, GLOBAL_SW_WARM_RST, ICEPICK_RST.
Source SYS_WARM_IN_RST is received over the input path from a dedicated device bidirectional pin.
The source is typically hardware generated via a reset push-button switch. Sources
SECURE_WD_RST and MPU_WDT_RST are generated from internal watchdog timer modules .
Activation is triggered by a timeout event. Source MPU_SECURITY_VIOL_RST is provided by the MPU
sub-system's Security State Machine. Activation is triggered upon detection of a security violation. This
is an active-high source. Source GLOBAL_WARM_SW_RST is a PRCM internally generated one.
Activation is triggered upon setting PRM memory-mapped register bit. This bit is self-clearing, i.e., it is
automatically cleared by the hardware.
1418
Power, Reset, and Clock Management (PRCM) Module
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Advertisement
Table of Contents
