Texas Instruments TMS320C6A816 Series Technical Reference Manual page 1564

C6-integra dsp+arm processors
Table of Contents

Advertisement

Introduction
16.1 Introduction
The serial ATA is the successor of the Parallel ATA/ATAPI controller that has served as the choice of
the communication medium between a portable computer (PC) and a hard-disk drive for several
decades. During these times, the PATA interface has gone through changes to sustain the demands of
the newly emerging applications needs and eventually reached its technical limitation creating a
throughput bound. The PATA controller reached a point where it required major changes to satisfy the
upcoming applications requirements and this led to its successor, the birth of the SATA controller. The
SATA controller was designed to use the same logical command structures that PATA uses but with a
whole new physical characteristic. The SATA controller makes use of 2 pairs of high-speed differential
conductors as opposed to the parallel 16 bit low-speed interface. The device has a built in SATA
controller with a dual HBA port operating in AHCI mode and is used to interface to data storage devices
at both 1.5 Gbits/Sec and 3.0 Gbits/Sec line speeds per HBA port. AHCI describes a system memory
structure which contains a generic area for control and status, and a table of entries describing a
command list where each command list entry contains information necessary to program an SATA
device, and a pointer to a descriptor table for transferring data between system memory and the device.
16.1.1 Purpose of the Peripheral
The SATA controller addresses the drawback of the PATA interface architecture, throughput, and
protocol perspectives. PATA required 40/80 wire parallel cable with a length requirement not exceeding
18 inches. With the latest/final PATA H/W design, PATA's maximum transfer rate saturated to a 133
Mbytes/Sec of transfer. In addition to newly added features, like hot swapping and native command
queuing, the SATA controller abandoned the parallel physical interface and transitioned to a high-speed
serial format using two differential pairs supporting up to 3 Mbits/Sec transfer rate, translating to a 300
Mbytes/Sec raw throughput per HBA port.
With the intent on handling roles of the PATA controller and addressing the future needs, SATA
controller is architected with the option of operating in a Legacy mode; a mode that behaves similar to
the PATA controller from the protocol/driver perspective, and a new AHCI mode that is different from
the Legacy mode allowing it to overcome the drawbacks of PATA protocol as well; extending PATAs
capabilities. The SATA controller that is supported by the device supports AHCI mode of operation only.
That is, the AHCI controller supported has no support for Legacy mode of operation. AHCI is a PCI
class device that acts as a data movement engine between system memory and Serial ATA devices.
However, the AHCI controller is integrated within the core chipset which usually is a common attribute
for embedded devices.
Communication between a device and software moves from the PATA task file registers access made
via byte-wide accesses to a structure based, command Frame Information Structure (FIS), located in
system memory that is fetched by the HBA. This reduces command setup time significantly, allowing for
many more devices to be added to a single host controller port (up to 15 of them via the use of a
hardware Port Multiplier). Software no longer communicates directly to a device via the task file. In
other words, all data transfers between the device and system memory occur through the HBA acting
as a bus master to system memory. Whether the transaction is of a DMA type or a PIO type (the use of
the PIO command type is strongly discouraged and all transfers should be performed using DMA
unless a transaction is only performed via PIO command, which in this case is still done via the AHCI
master port not the CPU), the HBA fetches and stores data to memory, offloading the CPU. No data
port exists for moving data in and out of the system memory similar to the PATA offerings. Software
written for AHCI is not allowed to utilize any of the legacy mechanisms to program devices.
The SATA controller uses a less massive thinner flexible cable that can be up to 3 feet (1 meter) in
length allowing for easier routing and better air ventilation inside a case. Its power budget is
significantly reduced to 250 mV compared to the required 5V and/or 3.3V power of PATA.
Like its predecessor the SATA controller is most commonly used by PCs, portable devices, and
embedded devices to interface a host processor with external data storage or CD/audio devices. It also
has the support for hot swapping capability and the ability of interfacing to a Port Multiplier (PM) to
increase the number of devices that can be attached to a single HBA port by as many as fifteen
devices. In other words, with the use of two PMs, a total of 30 devices can be connected to the two
available HBA ports. Note that in the case where a PM is used, the bandwidth offered by a single HBA
port will be shared amongst the total number of devices attached to the Port Multiplier. The device has
two HBA ports rendering aggregated 6Gbits/Sec throughput of raw data capability.
1564
Serial ATA (SATA) Controller
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
Submit Documentation Feedback

Advertisement

Table of Contents
loading

Table of Contents