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Table 16-32. Port Serial ATA Error Register (P#SERR) Field Descriptions (continued)
Bit
Field
Value
15-12
Reserved
0
11
ERR_E
0-1
10
ERR_P
0-1
9
ERR_C
0-1
8
ERR_T
0-1
7-2
Reserved
0
1
ERR_M
0-1
0
ERR_I
0-1
SPRUGX9 – 15 April 2011
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Preliminary
Description
Reserved.
Internal Error. This bit is set to 1 when one or more AHB bus ERROR responses are detected on the
master or the slave interfaces.
Protocol Error. This bit is set to 1 when any of the following conditions are detected:
• Transport state transition error (DIAG_T)
• Link sequence error (DIAG_S)
• RxFIFO overflow
• Link bad end error (WTRM instead of EOF is received)
Non-recovered Persistent Communication Error. This bit is set to 1 when the PHY Ready signal is
negated due to the loss of communication with the device or problems with the interface, but not after
transition from active to Partial or Slumber power management state.
Non-recovered Transient Data Integrity Error. This bit is set if any of the following P0SERR register bits
is set during Data FIS transfer:
• ERR_P (Protocol)
• DIAG_C (CRC)
• DIAG_H (Handshake)
• ERR_C (PHY Ready negation)
Reserved.
Recovered Communication Error. This bit is set to 1 when the PHY Ready condition is detected after
interface initialization, but not after transition from partial or Slumber power management state to active
state.
Recovered Data Integrity. This bit is set if any of the following P0SERR register bits is set during
non-Data FIS transfer:
• ERR_P (Protocol)
• DIAG_C (CRC)
• DIAG_H (Handshake)
• ERR_C (PHY Ready negation)
© 2011, Texas Instruments Incorporated
Registers
Serial ATA (SATA) Controller
1621
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