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Wake-up request from the SD/SDIO host controller
The idle acknowledgment varies according to the SD_SYSCONFIG[4:3] SIDLEMODE bit field:
•
0: Force-idle mode. The SD/SDIO host controller acknowledges the system power manager request
unconditionally.
•
1h: No-idle mode. The SD/SDIO host controller ignores the system power manager request and
behaves normally as if the request was not asserted.
•
2h: Smart-idle mode. The SD/SDIO host controller acknowledges the system power manager
request according to its internal state.
•
3h: Smart-idle wake-up-capable mode. The SD/SDIO host controller acknowledges the system
power manager request according to its internal state. However, the module may generate wake-up
events when in idle state ( related to IRQ or DMA requests)
During the smart-idle mode period, the SD/SDIO host controller acknowledges that the OCP and
Functional clocks may be switched off whatever the value set in the SD_SYSCONFIG[9:8]
CLOCKACTIVITY field.
9.2.3.3
Transition from Normal Mode to Smart-Idle Mode
Smart-idle mode is enabled when the SD_SYSCONFIG[4:3] SIDLEMODE bit field is set to 2h or 3h.
The SD/SDIO host controller goes into idle mode when the PRCM issues an idle request, according to
its internal activity. The SD/SDIO host controller acknowledges the idle request from the PRCM after
ensuring the following:
•
The current multi/single-block transfer is completed.
•
Any interrupt or DMA request is asserted.
•
There is no card interrupt on the SD_dat1 signal.
As long as the SD/SDIO controller does not acknowledge the idle request, if an event occurs, the
SD/SDIO host controller can still generate an interrupt or a DMA request. In this case, the module
ignores the idle request from the PRCM.
As soon as the SD/SDIO controller acknowledges the idle request from the PRCM:
•
If Smart-Idle modethe module does not assert any new interrupt or DMA request
•
If Smart-Idle wake-up-capable modethe module may generate wake-up events related to interrupt or
DMA request.
9.2.3.4
Transition from Smart-Idle Mode to Normal Mode
The SD/SDIO host controller detects the end of the idle period when the PRCM deasserts the idle
request. For the wake-up event, there is a corresponding interrupt status in the SD_STAT register. The
SD/SDIO host controller operates the conversion between wake-up and interrupt (or DMA request)
upon exit from smart-idle mode if the associated enable bit is set in the SD_ISE register.
Interrupts and wake-up events have independent enable/disable controls, accessible through the
SD_HCTL and SD_ISE registers. The overall consistency must be ensured by software.
The interrupt status register SD_STAT is updated with the event that caused the wake-up in the CIRQ
bit when the SD_IE[8] CIRQ_ENABLE associated bit is enabled. Then, the wake-up event at the origin
of the transition from smart-idle mode to normal mode is converted into its corresponding interrupt or
DMA request. (The SD_STAT register is updated and the status of the interrupt signal changes.)
When the idle request from the PRCM is deasserted, the module switches back to normal mode. The
module is fully operational.
9.2.3.5
Force-Idle Mode
Force-idle mode is enabled when the SD_SYSCONFIG[4:3] SIDLEMODE bit field is cleared to 0.
Force-idle mode is an idle mode where the SD/SDIO host controller responds unconditionally to the idle
request from the PRCM. Moreover, in this mode, the SD/SDIO host controller unconditionally deasserts
interrupts and DMA request lines are asserted.
SPRUGX9 – 15 April 2011
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Preliminary
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
© 2011, Texas Instruments Incorporated
Architecture
935
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