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Registers
Table 16-25. Port Interrupt Status Register (P#IS) Field Descriptions (continued)
Bit
Field
Value
7
DMPS
0-1
6
PCS
0
1
5
DPS
0-1
4
UFS
0-1
3
SDBS
0-1
2
DSS
0-1
1
PSS
0-1
0
DHRS
0-1
1612
Serial ATA (SATA) Controller
Preliminary
Description
Device Mechanical Presence Status. This bit is set when the state of SATA_MP_SWITCH input pin
changes as a result of a mechanical switch attached to this port being opened or closed. This bit is only
valid if both CAP.SMPS and P0CMD.MPSP are set to 1.
Port Connect Change Status. This bit reflects the state of the P0SERR.DIAG_X bit. This bit is only
cleared when P0SERR.DIAG_X is cleared.
No change in Current Connect Status
Change in Current Connect Status
Descriptor Processed. A PRD with the I bit set has transferred all of its data.
Note: This is an opportunistic interrupt and should not be used to definitely indicate the end of a
transfer. Two PRD interrupts could happen close in time together such that the second interrupt is
missed when the first PRD interrupt is being cleared.
Unknown FIS Interrupt. When set to 1, indicates that an unknown FIS was received and has been
copied into system memory. This bit is cleared to 0 by software clearing the P0SERR.DIAG_F bit to 0.
Note: The UFS bit does not directly reflect the P0SERR.DIAG_F bit. P0SERR.DIAG_F bit is set
immediately when an unknown FIS is detected, whereas the UFS bit is set when that FIS is posted to
memory. Software should wait to act on an unknown FIS until the UFS bit is set to 1 or the two bits may
become out of sync.
Set Device Bits Interrupt. A Set Device Bits FIS has been received with the I bit set and has been
copied into system memory.
DMA Setup FIS Interrupt. A DMA Setup FIS has been received with the I bit set and has been copied
into system memory.
PIO Setup FIS Interrupt. A PIO Setup FIS has been received with the I bit set, it has been copied into
system memory, and the data related to that FIS has been transferred.
Device to Host Register FIS Interrupt. A D2H Register FIS has been received with the I bit set, and has
been copied into system memory.
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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