Sata Core Block Diagram - Texas Instruments TMS320C6A816 Series Technical Reference Manual

Introduction
16.1.4 Functional Block Diagram
The SATASS is a fully contained Serial ATA host with built in DMA. It uses the AHCI standard for
communication with a SATA device. It has no support for the Legacy mode of operation.
shows a high level block diagram of the SATA Subsystem (core and the integrated TI PHY (SERDES)).
SERDES_CLKP
SERDES_CLKN
Interface
SATA_ACT0_LED
SATA_RXP0
SATA_RXN0
SATA_TXP0
SATA_TXN0
SATA_RXP1
PHY
SATA_RXN1
(SERDES/Draco)
SATA_TXP1
Interface
SATA_TXN1
SATA_ACT1_LED
VDD_SATA
VDDT_SATA
VSS_SATA
VSST_SATA
VDDR_15_SATA
16.1.5 Industry Standard(s) Compliance
The SATA Subsystem complies with the following industry standards:
• SATA revision 2.6 Gold standard.
• AHCI revision 1.1 specification.
16.1.6 Non-Industry Standard(s) Compliance
The SATA Subsytem complies with the following proprietary standards:
• Synopsys Design Ware Core DWC AHCI Controller Version 1.30.
• TI SERDES PHY: wiz7c2xxn5x1px (Draco) Macro specification Revision 01.02.01.
1566
Serial ATA (SATA) Controller
Figure 16-1. SATA Core Block Diagram
PHY
Link
Layer
RxFIFO
TxFIFO
PHY
Interface
Port Power Control Module
PHY
Link
Layer
RxFIFO
TxFIFO
PHY
Interface
Port Power Control Module
© 2011, Texas Instruments Incorporated
Preliminary
Port 0
Transport Port
Layer
DMA
Port
Registers
Port 1
Transport
Port
Layer
DMA
Port
Registers
www.ti.com
Figure 16-1
Bus
Interface
Unit
DMA
Interface
Register
Interface
Master
Interface
BIU
Master
Slave
Interface
BIU
Slave
DMA
Interface
Register
Interface
SPRUGX9 – 15 April 2011
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