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Introduction
13.1 Introduction
13.1.1 Overview
The PCI Express (PCIe) module is a multi-lane I/O interconnect that provides low pin count, high
reliability, and high-speed data transfer at rates of up to 5.0 Gbps per lane per direction, for serial links
on backplanes and printed wiring boards. It is a 3rd Generation I/O Interconnect technology succeeding
PCI and ISA bus that is designed to be used as a general-purpose serial I/O interconnect in multiple
market segments, including desktop, mobile, server, storage and embedded communications. It is also
used as a bridge to other interconnects like SATA, USB2/3.0, GbE MAC, etc.
The PCIESS contains the Synopsys DesignWare core (DWC) PCIe Dual Mode core and Texas
Instruments SERDES PHY. The Dual Mode (DM) core operates as either Endpoint (EP) mode or Root
Complex (RC) Port mode. The core supports a single In-Port and a single Out-Port. The role of the
PCIe core, EP or RC, is configured based on the value sampled from the BOOTMODE[4:0] pins and by
application software configuring PCIE_CFG[PCIE_DEVTYPE] register.
The incumbent design, PCI, is a parallel bus architecture that is increasingly difficult to scale-up in
bandwidth, which is usually performed by increasing the number of data signal lines. More signal lines
result in difficult clock-to-data skew management, creating complex PCB layout rules that make
cost-effective implementations in the FR4 technology difficult. Increasing the number of signal lines also
increases the power dissipation. The PCIe architecture was developed to help minimize I/O bus
bottlenecks within systems and to provide the necessary bandwidth for high-speed, chip-to-chip, and
board-to-board communications within a system. It is designed to replace the PCI-based shared,
parallel-bus-signaling technology that is approaching its practical performance limits while simplifying
the interface design. It includes cost, performance, and scalability advantages ensuring a long life span
existence to applications, system designs and investments.
PCIe is a serial-based technology which uses low-voltage differential data signaling/lines (LVDS) to
reduce the number of data signal lines and high-frequency clock signals in a point-to-point interconnect
arrangement between two devices. It also serves to eliminate multiple host presences on the same bus.
13.1.2 Features
The PCIESS on the device supports an interface width of ×2 lanes. The following features are included:
•
250 MHz functional clock frequency operation (PIPE clock frequency)
•
Supports a single bi-directional Link interface (i.e., a single Ingress and a single Egress ports) with a
maximum of 2 channels or two lanes width (x2)
•
Operates at a raw speed of 2.5Gbps or 5.0 Gbps per Lane per Direction
•
Maximum outbound payload size of 128 bytes
•
Maximum inbound payload size of 256 bytes
•
Maximum remote read request size of 256 bytes
•
Ultra-low transmit and receive latency
•
Support for dynamic-width conversion
•
Automatic Lane reversal
•
Polarity inversion on receive
•
Single Virtual Channel (VC)
•
Single Traffic Class (TC)
•
Automatic credit management
•
Single Function in Endpoint (EP) mode
•
ECRC generation and checking
•
PCI Device Power Management with the exception of D3 cold with Vaux
•
PCI Express Active State Power Management (ASPM) state L0s and L1
•
PCI Express Link Power Management states except L2 state
•
PCI Express Advanced Error Reporting
•
PCI Express messages for both transmit and receive
•
Filtering for Posted, Non-Posted, and Completion traffic
1272
Peripheral Component Interconnect Express (PCIe)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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