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20.3.2.4.1.3 Isochronous IN Error Handling: Host Mode
If a CRC or bit-stuff error occurs during the reception of a packet, the packet will still be stored in the
FIFO but the DATAERR_NAKTIMEOUT bit of HOST_RXCSR (bit 3) is set to indicate that the data may
be corrupt.
Note: The number of USB packets sent in any microframe will depend on the amount of data to be
transferred, and is indicated through the PIDs used for the individual packets. If the indicated numbers
of packets have not been received by the end of a microframe, the INCOMPRX bit in the
HOST_RXCSR register will be set to indicate that the data in the FIFO is incomplete. Equally, if a
packet of the wrong data type is received, then the PID Error bit is the HOST_RXCSR register will be
set. In each case, an interrupt will, however, still be generated to allow the data that has been received
to be read from the FIFO.
20.3.2.4.2 Isochronous OUT Transactions: Host Mode
An Isochronous OUT transaction may be used to transfer periodic data from the host to the USB
peripheral.
Following optional features are available for use with a Tx endpoint used in Host mode to transmit this
data:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting
transmission to the peripheral device. Double packet buffering is enabled by setting the DPB bit of
TXFIFOSZ register (bit 4).
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint is
able to accept another packet in its FIFO. This feature can be used to allow the DMA controller to load
packets into the FIFO without processor intervention.
However, this feature is not particularly useful with isochronous endpoints because the packets
transferred are often not maximum packet size.
When DMA is enabled and endpoint interrupt will not be generated for completion of packet reception.
Endpoint interrupt will be generated only in the error conditions.
20.3.2.4.2.1 Isochronous OUT Transfer Setup: Host Mode
Before initiating any Isochronous OUT transactions:
•
The target function address needs to be set in the TXFUNCADDR register for the selected controller
endpoint (TXFUNCADDR register is available for all endpoints from EP0 to EP4).
•
The HOST_TXTYPE register for the endpoint that is to be used needs to be programmed as:
– Operating speed in the SPEED bit field (bits 7 and 6).
– Set 01 (binary value) in the PROT field for isochronous transfer.
– Endpoint Number of the target device in TENDPN field. This is the endpoint number contained in
the OUT(Tx) endpoint descriptor returned by the target device during enumeration.
•
The TXMAXP register for the controller endpoint must be written with the maximum packet size (in
bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard
Endpoint Descriptor for the target endpoint.
•
The HOST_TXINTERVAL register needs to be written with the required transaction interval (usually
one transaction per frame/microframe).
•
The relevant interrupt enable bit in the INTRTXE register should be set (if an interrupt is required for
this endpoint).
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Protocol Description(s)
1793
Universal Serial Bus (USB)
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