Description; Ds160Pr412 And Ds160Pr421 4-Level I/O Control Inputs; Ds160Pr412 And Ds160Pr421 Modes Of Operation; Ds160Pr412 And Ds160Pr421 Smbus Or I2C Register Control Interface - Texas Instruments DS160PR412-421EVM User Manual

Evaluation module
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Description

2 Description

2.1 DS160PR412 and DS160PR421 4-Level I/O Control Inputs

Each DS160PR412 and DS160PR421 features 4-level input pins (MODE, GAIN/SDA, EQ0/ADDR, EQ1, and
RX_DET/SCL) that are used to control the configuration of the device. These 4-level inputs use a resistor divider
to help set the four valid levels to provide a wider range of control settings.

2.2 DS160PR412 and DS160PR421 Modes of Operation

Each DS160PR412 and DS160PR421 can be configured to operate in either Pin Mode, SMBus Mode, or I2C
Slave Mode. The mode of operation of the DS160PR412 and DS160PR421 is determined by the pin strap
setting on the MODE pin as shown in

2.3 DS160PR412 and DS160PR421 SMBus or I2C Register Control Interface

The DS160PR412 and DS160PR421 internal registers can be accessed through standard SMBus protocol. The
DS160PR412 and DS160PR421 features two banks of channels, Bank 0 (Channels 0-1) and Bank 1 (Channels
2-3), each featuring a separate register set and requiring a unique SMBus slave address. The SMBus slave
address pairs (one for each channel bank) are determined at power up based on the configuration of the MODE
and EQ0/ADDR pins. The pin state is read on power up, after the internal power-on reset signal is deasserted.
There are 8 unique SMBus slave address pairs (one address for each channel bank) that can be assigned to the
device by placing external resistor straps on the MODE and EQ0/ADDR pins as shown in
multiple DS160PR412 and DS160PR421 devices are on the same SMBus interface bus, each channel bank of
each device must be configured with a unique SMBus slave address pair.

Table 2-3. DS160PR412 and DS160PR421 SMBus Address Map

MODE
L1
L1
L1
L1
L2
L2
L2
L2
4
DS160PR412-421EVM Evaluation Module

Table 2-1. Four-Level Control Pin Settings

PIN LEVEL
L0
L1
L2
L3
Table
2-2.

Table 2-2. Modes of Operation

MODE PIN LEVEL
L0
L1
SMBus Mode or I2C Slave Mode
L2
SMBus Mode or I2C Slave Mode
L3
EQ0/ADDR Pin Level
7-Bit Address [HEX]
L0
L1
L2
L3
L0
L1
L2
L3
Copyright © 2020 Texas Instruments Incorporated
PIN SETTING
1 kΩ to GND
13 kΩ to GND
59 kΩ to GND
Float
MODE OF OPERATION
Pin Mode
RESERVED
Channels 0-1:
Channels 2-3:
7-Bit Address [HEX]
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
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Table
2-3. When
SNLU288 – DECEMBER 2020
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