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Introduction
20.1 Introduction
20.1.1 Overview
The USB controller provides a low-cost connectivity solution for numerous consumer portable devices
by providing a mechanism for data transfer between USB devices with a line/bus speed up to 480
Mbps. The device USB subsystem has two independent USB 2.0 Modules built around two OTG
controllers. Even though the controllers are OTG controllers, OTG features are not supported by any of
the ports. Each port has the support for a dual-role feature allowing for additional versatility enabling
operation capability as a host or peripheral. Both ports have identical capabilities and operate
independent of each other.
Each USB controller is built around the Mentor USB OTG controller (musbmhdrc) and Synopsys
SR70LX PHY. Each USB controller has user configurable 32K Bytes of Endpoint FIFO and has the
support for 15 'Transmit' endpoints and 15 'Receive' endpoints in addition to Endpoint 0. The USB
subsystem makes use of the CPPI 4.1 DMA for accelerating data movement via a dedicated DMA
hardware.
The two USB modules share the CPPI DMA controller and accompanying Queue Manager, Interrupt
Pacer, Power Management module, and PHY/UTMI clock.
Within the descriptions of the USB subsystem that would follow, the term USB controller or USB PHY is
used to mean/refer to any of the two USB controllers or PHYs existing within the USB subsystem. The
term USB module is used to mean/refer to any of the two USB modules. USB0(1) is used to refer to
one of the two USB Modules.
20.1.2 Acronyms, Abbreviations, and Definitions
AHB
CBA
CDC
CPPI
CPU
DFT
DMA
DV
EOI
EOP
FIFO
FS
HNP
HS
INTD
IP
ISO
LS
MHz
MP[
OCP
OCP HD
OCP MMR
OTG
PDR
PHY
1752
Universal Serial Bus (USB)
Preliminary
Advanced High-Performance Bus
Common Bus Architecture
Change Data Capture
Communications Port Programming Interface
Central Processing Unit
Design for Test
Direct Memory Access
Design Verification
End of Interrupt
End of Packet
First-In First-Out
Full-Speed USB Data Rate
Host Negotiation
High-Speed USB Data Rate
Interrupt Distributor
Intellectual Property
Isochronous transfer type
Low-Speed USB data rate
Megahertz
Middle of Packet
Open Core Protocol
OCP High Performance
OCP Memory Mapped Registers
On-The-Go
Physical Design Requirements
Physical Layer Device
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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