Texas Instruments TMS320C6A816 Series Technical Reference Manual page 887

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Table 7-23. I2C Configuration Register (I2C_CON) Field Descriptions (continued)
Bit Field Value
9 TRX
8 XSA
7 XOA0
6 XOA1
5 XOA2
4 XOA3
3-2 Reserved
1 STP
SPRUGX9 – 15 April 2011
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Preliminary
Description
Transmitter/receiver mode (i2C master mode only). When this bit is cleared, the I2C controller is in
the receiver mode and data on data line SDA is shifted into the receiver FIFO and can be read from
I2C_DATA register. When this bit is set, the I2C controller is in the transmitter mode and the data
written in the transmitter FIFO via I2C_DATA is shifted out on data line SDA.
0 Receiver mode
1 Transmitter mode
Value after reset is low.
The operating modes are defined as follows:
MST TRX
0 x
0 x
1 0
1 1
Expand slave address. (I2C mode only). When set, this bit expands the slave address to 10-bit.
0 7-bit address mode
1 10-bit address mode
Value after reset is low.
Expand own address 0. (I2C mode only). When set, this bit expands the base own address (OA0) to
10-bit.
0 7-bit address mode
1 10-bit address mode
Value after reset is low.
Expand own address 1. (I2C mode only). When set, this bit expands the first alternative own
address (OA1) to 10-bit.
0 7-bit address mode
1 10-bit address mode
Value after reset is low.
Expand own address 2. (I2C mode only). When set, this bit expands the second alternative own
address (OA2) to 10-bit.
0 7-bit address mode. (I2C mode only).
1 10-bit address mode
Value after reset is low.
Expand own address 3. When set, this bit expands the third alternative own address (OA3) to 10-bit.
0 7-bit address mode
1 10-bit address mode
Value after reset is low.
0 Reserved
Stop condition (I2C master mode only). This bit can be set to a 1 by the CPU to generate a stop
condition. It is reset to 0 by the hardware after the stop condition has been generated. The stop
condition is generated when DCOUNT passes 0.
When this bit is not set to 1 before the end of the transfer (DCOUNT = 0), the stop condition is not
generated and the SCL line is hold to 0 by the master, which can re-start a new transfer by setting
the STT bit to 1.
0 No action or stop condition detected
1 Stop condition queried
Value after reset is low
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Operating Modes
Slave receiver
Slave transmitter
Master receiver
Master transmitter
Inter-Integrated Circuit (I2C) Controller Module
Registers
887