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Communications Port Programming Interface (CPPI) 4.1 DMA
20.4.5 Zero Length Packets
A special case is the handling of null packets with the CPPI 4.1 compliant DMA controller. Upon
receiving a zero length USB packet, the XFER DMA will send a data block to the DMA controller with
byte count of zero and the zero byte packet bit of INFO Word 2 set. The DMA controller will then
perform normal End of Packet termination of the packet, without transferring data.
If a zero-length USB packet is received, the XDMA will send the CDMA a data block with a byte count
of 0 and this bit set. The CDMA will then perform normal EOP termination of the packet without
transferring data. For transmit, if a packet has this bit set, the XDMA will ignore the CPPI packet size
and send a zero-length packet to the USB controller.
20.4.6 CPPI DMA Scheduler
The CPPI DMA scheduler is responsible for controlling the rate and order between the different Tx and
Rx threads/transfers that are provided in the CPPI DMA controller. The scheduler table RAM exists
within the scheduler.
The DMA controller maintains state information for each of the channels which allows packet
segmentation and reassembly operations to be time division multiplexed between channels in order to
share the underlying DMA hardware. A DMA scheduler is used to control the ordering and rate at which
this multiplexing occurs.
20.4.6.1 CPPI DMA Scheduler Operation
Once the scheduler is enabled it will begin processing the entries in the table. When appropriate the
scheduler will pass credits to the DMA controller to perform a Tx or Rx operation. The operation of the
DMA controller is as follows:
1. After the DMA scheduler is enabled it begins with the table index set to 0.
2. The scheduler reads the entry pointed to by the index and checks to see if the channel in question
is currently in a state where a DMA operation can be accepted.
(a) The DMA channel must be enabled AND
(b) The CPPI FIFO that the channel talks to has free space on TX (FIFO full signal is not asserted)
or a valid block on Rx (FIFO empty signal is not asserted)
3. If the DMA channel is capable of processing a credit to transfer a block, the DMA scheduler will
issue that credit via the DMA scheduling interface which is a point to point connection between the
DMA Scheduler and the DMA Controller.
(a) The DMA controller may not be ready to accept the credit immediately and is provided a
sched_ready signal which is used to stall the scheduler until it can accept the credit. The DMA
controller only asserts the sched_ready signal when it is in the IDLE state.
(b) Once a credit has been accepted (indicated by sched_req and sched_ready both asserted), the
scheduler will increment the index to the next entry and will start again at step 2.
4. If the channel in question is not currently capable of processing a credit, the scheduler will
increment the index in the scheduler table to the next entry and will start at step 2.
5. Note that when the scheduler attempts to increment its index, to the value programmed in the table
size register, the index will be reset to 0.
20.4.6.1.1 CPPI DMA Scheduler Initialization
Before the scheduler can be used, the host is required to initialize and enable the block. This
initialization is performed as follows:
1. The Host initializes entries within an internal memory array in the scheduler. This array contains up
to 256 entries (4 entries per table word n where n=0-63) and each entry consists of a DMA channel
number and a bit indicating if this is a Tx or Rx opportunity. These entries represent both the order
and frequency that various Tx and Rx channels will be processed. A table size of 256 entries allows
channel bandwidth to be allocated with a maximum precision of 1/256th of the total DMA bandwidth.
The more entries that are present for a given channel, the bigger the slice of the bandwidth that
channel will be given. Larger tables can be accommodated to allow for more precision. This array
can only be written by the Host, it cannot be read.
1808
Universal Serial Bus (USB)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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