Table of Contents
Advertisement
Reset Considerations
20.5.5 FIFO_ACCESS
The FIFO Access test mode allows you to test the operation of CPU Interface, the DMA controller (if
configured), and the RAM block by loading a packet of up to 64 bytes into the Endpoint 0 FIFO and
then reading it back out again. Endpoint 0 is used because it is a bidirectional endpoint that uses the
same area of RAM for its Tx and Rx FIFOs.
NOTE: The core does not need to be connected to the USB bus to run this test. If it is connected, then
no session should be in progress when the test is run.
The test procedure is as follows:
1. Load a packet of up to 64 bytes into the Endpoint 0 Tx FIFO.
2. Set HOST/PERI_CSR0[TXPKTRDY].
3. Write 40h to the TESTMODE register (FIFO_ACCESS = 1).
4. Unload the packet from the Endpoint Rx FIFO, again.
5. Set HOST/PERI_CSR0[SERVICEDRXPKTRDY].
Writing 40h to the TESTMODE register causes the following sequence of events:
The Endpoint 0 CPU pointer (that records the number of bytes to be transmitted) is copied to the
Endpoint 0 USB pointer (that records the number of bytes received).
1. The Endpoint 0 CPU pointer is reset.
2. HOST/PERI_CSR0[TXPKTRDY] is cleared.
3. HOST/PERI_CSR0[RXPKTRDY] is set.
4. An Endpoint 0 interrupt is generated (if enabled).
The effect of these steps is to make the Endpoint 0 controller act as if the packet loaded into the Tx
FIFO has flushed and the same packet received over the USB. The data that was loaded in the Tx
FIFO can now be read out of the Rx FIFO.
20.5.6 FORCE_HOST
The Force Host test mode enables you to instruct the core to operate in Host mode, regardless of
whether it is actually connected to any peripheral; that is, the state of the CID input and the LINESTATE
and HOSTDISCON signals are ignored. (While in this mode, the state of the HOSTDISCON signal can
be read from the BDEVICE bit in the device control register (DEVCTL)) .
This mode, which is selected by writing 80h to the TESTMODE register (FORCE_HOST = 1), allows
implementation of the USB Test_Force_Enable (USB 2.0 Specification Section 7.1.20). It can also be
used for debugging PHY problems in hardware.
While the FORCE_HOST bit remains set, the core enters the Host mode when the SESSION bit in
DEVCTL is set to 1 and remains in the Host mode until the SESSION bit is cleared to 0 even if a
connected device is disconnected during the session. The operating speed while in this mode is
determined by the FORCE_HS and FORCE_FS bits in the TESTMODE register.
20.6 Reset Considerations
The USB controller has two reset sources: hardware reset and the soft reset.
20.6.1 Software Reset Considerations
When the RESET bit in the control register (CTRLR) is set, all the USB controller registers and DMA
operations are reset. The bit is cleared automatically.
A software reset on the DSP or ARM CPU does not affect the register values and operation of the USB
controller.
20.6.2 Hardware Reset Considerations
When a hardware reset is asserted, all the registers are set to their default values.
1820
Universal Serial Bus (USB)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Advertisement
Table of Contents
