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Architecture
9.2.2.2
Software Reset
The module is reinitialized by software through the SD_SYSCONFIG[1] SOFTRESET bit. This bit has
the same action on the module logic as the hardware signal except for:
•
Debounce logic
•
SD_PSTATE, SD_CAPA, and SD_CUR_CAPA registers (see corresponding register descriptions)
The SOFTRESET bit is active high. The bit is automatically reinitialized to 0 by the hardware. The
SD_SYSCTL[24] SRA bit has the same action as the SOFTRESET bit on the design.
The SD_SYSSTATUS[0] RESETDONE bit can be monitored by the software to check if the module is
ready-to-use after a software reset.
Moreover, two partial software reset bits are provided:
•
SD_SYSCTL[26] SRD bit
•
SD_SYSCTL[25] SRC bit
These two reset bits are useful to reinitialize data or command processes respectively in case of line
conflict. When set to 1, a reset process is automatically released when the reset completes:
•
The SD_SYSCTL[26] SRD bit resets all finite state-machines and status management that handle
data transfers on both the interface and functional side.
•
The SD_SYSCTL[25] SRC bit resets all finite state-machines and status management that handle
command transfers on both the interface and functional side.
NOTE: If any of the clock inputs are not present for the SD/SDIO peripheral, the software reset
will not complete.
9.2.3 Power Management
The SD/SDIO host controller can enter into different modes and save power:
•
Normal mode
•
Idle mode
The two modes are mutually exclusive (the module can be in normal mode or in idle mode). The
SD/SDIO host controller is compliant with the PRCM module handshake protocol. When the SD/SDIO
power domain is off, the only way to wake up the power domain and different SD/SDIO clocks is to
monitor the SD_DAT1 input pin state via a different GPIO line for each SD/SDIO interface.
9.2.3.1
Normal Mode
The autogating of interface and functional clocks occurs when the following conditions are met:
•
The SD_SYSCONFIG[0] AUTOIDLE bit is set to 1.
The autogating of interface and functional clocks stops when the following conditions are met:
•
A register access occurs through the L3 (or L4) interconnect.
•
A wake-up event occurs (an interrupt from a SDIO card).
•
A transaction on the SD/SDIO interface starts.
Then the SD/SDIO host controller enters in low-power state even if SD_SYSCONFIG[0] AUTOIDLE is
cleared to 0. The functional clock is internally switched off and only interconnect read and write
accesses are allowed.
9.2.3.2
Idle Mode
The clocks provided to SD/SDIO are switched off upon a PRCM module request. They are switched
back upon module request. The SD/SDIO host controller complies with the PRCM module handshaking
protocol:
•
Idle request from the system power manager
•
Idle acknowledgment from the SD/SDIO host controller
934
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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