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•
Configurable BAR filtering, I/O filtering, configuration filtering and Completion lookup/timeout
•
Access to configuration space registers and external application memory mapped registers through
BAR0 and through configuration access
•
Legacy Interrupts reception (Root Complex (RC)) and generation (EP)
•
MSI generation and reception
•
PHY Loopback in RC mode
13.1.3 Features Not Supported
The following features are not supported by the PCIESS:
•
Multiple VCs
•
Multiple TCs
•
Function Level Reset
•
PCI Express beacon for in-band wake
•
Built-in hardware support for hot plug
•
Vendor Messaging
•
IO access in inbound direction
•
Addressing modes other than incremental for burst transactions
•
Using ×2 link as two ×1 links
•
Auxiliary Power to maintain controller state to come out D3cold state
•
Link state L2 support
13.1.4 Functional Block Diagram
The PCIESS is shown in
13.1.4.1 PCIe Core
The PCI Express core implements the three PCI Express protocol layers (Transaction Layer, Data Link
Layer, and the MAC portion of the Physical Layer). The PCIe core is a Dual Mode core allowing it to
operate either as an RC or as an EP. As an EP, it can operate as a Legacy Endpoint or native PCIe
Endpoint. The role it assumes is based on the state of the PCIe Configuration register (within the
Control Module) bit field PCIE_DEVTYPE. PCIE_CFG.DEVTYPE = 00b/ 01b/ 10b = EP/ Legacy
Endpoint/ RC respectively. The user software or BOOTROM is required to initialize this field. During
times PCIe is used as a Boot Device, then the state of Bootmode Pins will determine the Boot Type
used (in this case it will be PCIe) and the address size to be used which is either 32bit or 64bit
addressing. The bootloader software configures the PCIe core to operate in EP mode. No RC
Bootmode is supported.
13.1.4.2 PCIe PHY
The PCI PHY (SERDES) contains the analog portion of the PHY which is the transmission line channel
that is used to transmit and receive data. It contains a phase locked loop, analog transceiver, phase
interpolation based clock/data recovery, parallel to serial converter, serial to parallel converter,
scrambler, configuration and test logic.
13.1.4.3 OCP (Configuration and DMA Access Interface)
CPU side access, Configuration Registers, Data Access, and Remote EP DMA access is performed
through the Configuration and DMA Access interface. The maximum amount of data burst access made
through this port is 128 bytes.
SPRUGX9 – 15 April 2011
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Preliminary
Figure
13-1.
© 2011, Texas Instruments Incorporated
Peripheral Component Interconnect Express (PCIe)
Introduction
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