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12.2.3.2 Interrupt Events in Master Mode
In master mode, the interrupt events related to the transmitter register state are TX_empty and
TX_underflow. The interrupt event related to the receiver register state is RX_full.
12.2.3.2.1 TX_empty
The event TX_empty is activated when a channel is enabled and its transmitter register becomes empty
(transient event). Enabling channel automatically raises this event, except for the Master receive only
mode. (See
Section
TX_empty is asserted as soon as there is enough space in buffer to write a number of byte defined by
MCSPI_XFERLEVEL[AEL].
Transmitter register must be loaded to remove the source of the interrupt and the TX_empty interrupt
status bit must be cleared for interrupt line de-assertion (if event enabled as interrupt source) . (See
Section
12.2.5).
When FIFO is enabled, no new TX_empty event will be asserted as soon as CPU has not performed
the number of write into transmitter register defined by MCSPI_XFERLEVEL[AEL]. It is the
responsibility of CPU to perform the right number of writes.
12.2.3.2.2 TX_underflow
The event TX_underflow is activated when the channel is enabled and if the transmitter register or
FIFO is empty (not updated with new data) at the time of shift register assignment.
The TX_underflow is a harmless warning in master mode.
To avoid having TX_underflow event at the beginning of a transmission, the event TX_underflow is not
activated when no data has been loaded into the transmitter register since channel has been enabled.
To avoid having TX_underflow event the Transmitter register must be loaded seldom.
TX_underflow interrupt status bit must be cleared for interrupt line de-assertion (if event enable as
interrupt source).
Note: Be careful, when more than one channel have a FIFO enable bit field FFER or FFEW set, the
module force no use of FIFO, software must take care that only one enabled channel is configured to
use the FIFO buffer.
12.2.3.2.3 RX_ full
The event RX_full is activated when channel is enabled and receiver register becomes filled (transient
event). When FIFO buffer is enabled (MCSPI_CH(I)CONF[FFER] set to 1), the RX_full is asserted as
soon as there is a number of bytes holds in buffer to read defined by MCSPI_XFERLEVEL[AFL].
Receiver register must be read to remove source of interrupt and RX_full interrupt status bit must be
cleared for interrupt line de-assertion (if event enabled as interrupt source).
When FIFO is enabled, no new RX_full event will be asserted as soon as CPU has not performed the
number of read into receive register defined by MCSPI_XFERLEVEL[AFL]. It is the responsibility of
CPU to perform the right number of reads.
12.2.3.2.4 End of Word Count
The event end of word count (EOW) is activated when channel is enabled and configured to use the
built-in FIFO. This interrupt is raised when the controller had performed the number of transfer defined
in MCSPI_XFERLEVEL[WCNT] register. If the value was programmed to 0000h, the counter is not
enabled and this interrupt is not generated.
The End of Word count interrupt also indicates that the SPI transfer is halt on channel using the FIFO
buffer as soon as MCSPI_XFERLEVEL[WCNT] is not reloaded and channel re-enabled.
End of Word interrupt status bit must be cleared for interrupt line de-assertion (if event enable as
interrupt source).
SPRUGX9 – 15 April 2011
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Preliminary
12.2.3.5). When FIFO buffer is enabled (MCSPI_CH(I)CONF[FFEW] set to 1), the
© 2011, Texas Instruments Incorporated
Multichannel Serial Port Interface (McSPI)
Architecture
1223
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