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Data behavior:
1. Choose 1 or 2 phases for the transmit frame.
2. Set the transmit word length(s).
3. Set the transmit frame length (one word per phase if dual-phase selected).
4. Enable/disable the transmit frame–synchronization ignore function.
5. Set the transmit data delay.
6. Set the transmit DXENA mode.
7. Set the transmit interrupt mode.
Frame-synchronization behavior:
1. Set the transmit frame–synchronization mode.
2. Set the transmit frame–synchronization polarity.
3. Set the SRG frame–synchronization period and pulse width.
Clock behavior:
1. Set the transmit clock mode.
2. Set the transmit clock polarity.
3. Set the SRG clock divide–down value.
4. Set the SRG clock synchronization mode.
5. Set the SRG clock mode (choose an input clock).
6. Set the SRG input clock polarity.
11.2.8.6.2 Resetting and Enabling the Transmitter
The first step of the transmitter configuration procedure is to reset the transmitter, and the last step is to
enable the transmitter (to take it out of reset). The serial port can be reset in the following two ways:
1. A global reset places the receiver, transmitter, and sample rate generator in reset. When the device
reset is removed, GRST, FRST, RRST and XRST bits = 0, keeping the entire serial port in the reset
state.
2. The serial port transmitter and receiver can be reset directly using the RRST and XRST bits in the
SPCR1_REG register. The sample rate generator can be reset directly using the GRST bit in
SPCR2_REG register.
11.2.8.6.3 Set the Transmitter Pins to Operate as McBSP Pins
The XIOEN bit (PCR_REG[13]) determines whether the transmitter pins are McBSP pins or
general–purpose I/O pins.
11.2.8.6.4 Enable/Disable the Digital Loop Back Mode
The DLB bit (XCCR_REG) determines whether the digital loop-back mode is on or off. In the digital
loop-back mode, the receive signals are connected internally through multiplexers to the corresponding
transmit signals (DR is connected to transmit data on DX output pin DXO, FSR is connected to FRX
output pin FSXO, and CLKR is connected to the CLKX output pin CLKXO). This mode allows testing of
serial port; the McBSP receives the data it transmits. This loop back mode is not done through pads, all
output signals being disabled (CLKREN, CLKXEN, FSREN, FSRXEN, DXEN are not active).
Note that in digital loop back mode the sample rate generator and the frame synchronization generator
need to be enabled in order to generate the CLKX and FSX signals.
11.2.8.6.5 Enable/Disable the Transmit Multichannel Selection
The XMCM bit field (MCR2_REG[1:0]) determines whether the transmit multichannel selection mode is
on or off.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
Architecture
1167
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