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Figure 10-25. Processor Service Time Upon Transmit DMA Event (AXEVT)
ACLKX
AXR
A1
A0
B15 B14 B13 B12 B11 B10
AXEVT
AXEVT
Latency
(for Word C)
5 McASP
(A)
system clocks
A
Refer to the device-specific data manual for the McASP system clock source. This is not the same as AUXCLK.
Example 10-1. Processor Service Time Calculation for Transmit DMA Event (AXEVT)
The following is an example to show how to calculate Processor Service Time. Assume the following setup:
•
Device: C64x+ DSP at 300 MHz.
•
McASP transmits in I2S format at 192 kHz frame rate. Assume slot size is 32 bit.
With the above setup, we obtain the following parameters corresponding to
•
Calculation of McASP system clock cycle:
– C64x+ DSP uses SYSCLK2 as the McASP system clock. It runs at 150 MHz (half of device frequency).
– Therefore, McASP system clock cycle = 1/150 MHz = 6.7 ns.
•
Calculation of ACLKX clock cycle:
– This example has two 32-bit slots per frame, for a total of 64 bits per frame.
– ACLKX clock cycle is (1/192 kHz)/64 = 81.4 ns.
•
Time Slot between AXEVT events:
– For I2S format, McASP generates two AXEVT events per 192 kHz frame.
– Therefore, Time Slot between AXEVT events is (1/192 kHz)/2 = 2604 ns.
•
AXEVT Latency:
= 5 McASP system clocks
= 6.7 ns × 5 = 33.5 ns
•
Setup Time
= 3 McASP system clocks + 4 ACLKX cycles
= (6.7 ns × 3) + (81.4 ns × 4)
= 345.7 ns
•
Processor Service Time
= Time Slot - AXEVT Latency - Setup Time
= 2604 ns - 33.5 ns - 345.7 ns
= 2225 ns
SPRUGX9 – 15 April 2011
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Preliminary
N ACLKX cycles (N=number of bits in slot)
B9
B8
B7
Service time
(to write Word C)
© 2011, Texas Instruments Incorporated
B6
B5
B4
B3
B2
B1
Setup time
(for Word C)
3 McASP
system clocks +
4 ACLKX cycles
Figure
10-25:
Multichannel Audio Serial Port (McASP)
Architecture
B0
C15
1041
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