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Architecture
11.2.2.2.3 Keeping FSG Synchronized to an External Clock
When an external signal is selected to drive the sample rate generator, the GSYNC bit of
SRGR2_REG15] register and the McBSP.FSR pin can be used to configure the timing of FSG pulses.
GSYNC = 1 ensures that the McBSP and an external device are dividing down the input clock with the
same phase relationship. If GSYNC = 1, an inactive–to–active transition on the McBSP.FSR pin triggers
a resynchronization of CLKG and generation of FSG.
11.2.2.3 Synchronizing Sample Rate Generator Outputs to an External Clock
The sample rate generator can produce a clock signal (CLKG) and a frame–synchronization signal
(FSG) based on an input clock signal that is either the FCLK functional clock signal or a signal at the
McBSP.CLKS, McBSP.CLKR, or McBSP.CLKX pin. When an external clock is selected to drive the
sample rate generator, the GSYNC bit of SRGR2_REG[15] register and the McBSP.FSR pin can be
used to control the timing of CLKG and the pulsing of FSG relative to the chosen input clock.
Make GSYNC = 1 when you want the McBSP and an external device to divide down the input clock
with the same phase relationship. If GSYNC = 1:
•
An inactive–to–active transition on the McBSP.FSR pin triggers a resynchronization of CLKG and a
pulsing of FSG.
•
CLKG always begins with a high state after synchronization.
•
FSR is always detected at the same edge of the input clock signal that generates CLKG, no matter
how long the FSR pulse is.
•
The SRGR2_REG[11:0] register FPER bits are ignored because the frame–synchronization period
on FSG is determined by the arrival of the next frame–synchronization pulse on the McBSP.FSR
pin.
If GSYNC = 0, CLKG runs freely and is not resynchronized, and the frame–synchronization period on
FSG is determined by FPER.
11.2.2.3.1 Operating the Transmittor Synchronously with the Receiver
When GSYNC = 1, the transmitter can operate synchronously with the receiver, provided that:
•
FSX is programmed to be driven by FSG (FSGM = 1 in SRGR2_REG[12] register and FSXM = 1 in
PCR_REG[11] register). If the input FSR has appropriate timing so that it can be sampled by the
falling edge of CLKG, it can be used, instead, by setting FSXM = 0 and connecting FSR to FSX
externally.
•
The sample rate generator clock drives the transmit and receive clocking (PCR_REG[8] CLKRM bit
and PCR_REG[9] CLKXM bit are set to 1). Therefore, the CLK(R/X) pin must not be driven by any
other driving source.
11.2.2.3.2 Synchronization Examples
Figure 11-12
and
polarities of CLKS (the chosen input clock) and FSR. These figures assume FWID = 0 in
SRGR1_REG[15:8] register, for an FSG pulse that is one CLKG cycle wide. The FPER bits of
SRGR2_REG[11:0] register are not programmed; the period from the start of a frame–synchronization
pulse to the start of the next pulse is determined by the arrival of the next inactive–to–active transition
on the McBSP.FSR pin. Each of the figures shows what happens to CLKG when it is initially
synchronized and GSYNC = 1, and when it is not initially synchronized and GSYNC = 1.
has a slower CLKG frequency (it has a larger divide–down value in the CLKGDV bits of
SRGR1_REG[7:0] register).
1136
Multichannel Buffered Serial Port (McBSP)
Preliminary
Figure 11-13
show the clock and frame–synchronization operation with various
© 2011, Texas Instruments Incorporated
www.ti.com
Figure 11-13
SPRUGX9 – 15 April 2011
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