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Table 11-2. Effects of DLB and ALB Bits on Clock Modes (continued)
CLKXM = 1
11.2.2.2 Frame Sync Generation in the Sample Rate Generator
The sample rate generator can produce a frame–synchronization signal (FSG) for use by the receiver,
the transmitter, or both.
If you want the receiver to use FSG for frame synchronization, make sure PCR_REG[10] register
FSRM bit = 1. (When FSRM = 0, receive frame synchronization is supplied via the McBSP.FSR pin.)
If you want the transmitter to use FSG for frame synchronization, you must set:
•
FSXM = 1 in PCR_REG[11] register: This indicates that transmit frame synchronization is supplied
by the McBSP itself rather than from the McBSP.FSX pin
•
FSGM = 1 in SRGR2_REG[12] register: This indicates that when FSXM = 1, transmit frame
synchronization is supplied by the sample rate generator. (When FSGM = 0 and FSXM = 1, the
transmit frame-sync signal (FSX) is generated when transmit buffer is not empty. When FSGM = 0,
FPER and FWID are used to determine the frame synchronization period and width (external FSX is
gated by the buffer empty condition).
In either case, the sample rate generator must be enabled (SPCR2_REG[6] register GRST bit = 1) and
the frame–synchronization logic in the sample rate generator must be enabled (SPCR2_REG[7] register
FRST bit = 0).
11.2.2.2.1 Choosing the Width of the Frame-Sync Pulse
Each pulse on FSG has a programmable width. You program the SRGR1_REG[15:8] register FWID
bits, and the resulting pulse width is (FWID + 1) CLKG cycles, where CLKG is the output clock of the
sample rate generator.
11.2.2.2.2 Controlling the Period Between the Starting Edges of the Frame-Sync Pulses
You can control the amount of time from the starting edge of one FSG pulse to the starting edge of the
next FSG pulse. This period is controlled in one of two ways, depending on the configuration of the
sample rate generator:
•
If the sample rate generator is using an external input clock and SRGR2_REG[15] register GSYNC
bit = 1, FSG pulses in response to an inactive–to–active transition on the McBSP.FSR pin. Thus, an
external device controls the frame–synchronization period.
•
Otherwise, you program the FPER bits of SRGR2_REG[11:0] register, and the resulting
frame–synchronization period is (FPER + 1) CLKG cycles, where CLKG is the output clock of the
sample rate generator.
SPRUGX9 – 15 April 2011
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Mode Bit Settings
DLB = 0 & ALB = 0
(Digital & analog loop back mode
disabled)
DLB = 0 & ALB = 1
(Analog loop back mode enabled)
DLB = 1 & ALB = 0
(Digital loop back mode enabled)
DLB = 1 & ALB = 1 (reserved mode)
ALBRXCTRL[0] = 1
(synchronous mode DLB = 0 & ALB = 0)
© 2011, Texas Instruments Incorporated
Preliminary
CLKX is an output pin driven by the sample rate generator
output clock (CLKG).
CLKX is an output pin driven by the sample rate generator
output clock (CLKG).
CLKX is not driven.
The sample rate generator and the frame synchronization
generator need to be enabled.
The internal transmit and receive clocks are driven by SRG
(CLKG having the appropriate CLKXP polarity).
The transmit and receive frame synchronization signals are
driven by FSG (having the appropriate FSXP polarity).
The transmit data is connected to the receive input data.
Note that in digital loop back mode no serial link activity will be
seen by the remote device because CLKREN, CLKXEN,
FSREN, FSRXEN, DXEN are not active.
Undefined functionality.
CLKX is an output pin driven by the sample rate generator
output clock (CLKG). CLKR is connected to the CLKX.
Multichannel Buffered Serial Port (McBSP)
Architecture
Effect
1135
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