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8.2.4 Module Power Saving
The INTC provides an auto-idle function in its three clock domains:
•
Interface clock
•
Functional clock
•
Synchronizer clock
The interface clock auto-idle power-saving mode is enabled if the INTCPS_SYSCONFIG[0] AUTOIDLE
bit is set to 1. When this mode is enabled and there is no activity on the bus interface, the interface
clock is disabled internally to the module, thus reducing power consumption. When there is new activity
on the bus interface, the interface clock restarts without any latency penalty. After reset, this mode is
disabled, by default. The functional clock auto-idle power-saving mode is enabled if the
INTCPS_IDLE[0] FUNCIDLE bit is cleared to 0. When this mode is enabled and there is no active
interrupt (IRQ or FIQ interrupt being processed or generated) or no pending incoming interrupt, the
functional clock is disabled internally to the module, thus reducing power consumption. When a new
unmasked incoming interrupt is detected, the functional clock restarts and the INTC processes the
interrupt. If this mode is disabled, the interrupt latency is reduced by one cycle. After reset, this mode is
enabled, by default. The synchronizer clock allows external asynchronous interrupts to be
resynchronized before they are masked. The synchronizer input clock has an auto-idle power-saving
mode enabled if the INTCPS_IDLE[1] TURBO bit is set to 1. If the auto-idle mode is enabled, the
standby power is reduced, but the IRQ or FIQ interrupt latency increases from four to six functional
clock cycles. This feature can be enabled dynamically according to the requirements of the device.
After reset, this mode is disabled, by default.
8.2.5 Error Handling
The following accesses will cause error:
•
Privilege violation (attempt to access PROTECTION register in user mode or any register in user
mode if Protection bit is set).
•
Unsupported commands.
The following will NOT cause any error response:
•
Access to a non-decoded address.
•
Write to a read-only register.
8.2.6 Interrupt Latency
The IRQ/FIQ interrupt generation takes four INTC functional clock cycles (plus or minus one cycle) if
the INTCPS_IDLE[1] TURBO bit is cleared to 0. If the TURBO bit is set to 1, the interrupt generation
takes six cycles, but power consumption is reduced while waiting for an interrupt. These latencies can
be reduced by one cycle by disabling functional clock auto-idle (INTCPS_IDLE[0] FUNCIDLE bit set to
1), but power consumption is increased, so the benefit is minimal. To minimize interrupt latency when
an unmasked interrupt occurs, the IRQ or FIQ interrupt is generated before priority sorting completion.
The priority sorting takes 10 functional clock cycles, which is less than the minimum number of cycles
required for the MPU to switch to the interrupt context after reception of the IRQ or FIQ event.
Any read of the INTCPS_SIR_IRQ or INTCPS_SIR_FIQ register during the priority sorting process
stalls until priority sorting is complete and the relevant register is updated. However, the delay between
the interrupt request being generated and the interrupt service routine being executed is such that
priority sorting always completes before the INTCPS_SIR_IRQ or INTCPS_SIR_FIQ register is read.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Architecture
907
Interrupt Controller
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