Table of Contents
Advertisement
Architecture
•
AFSXCTL: Configure the bits according to the discussion in this section.
•
ACLKXCTL: ASYNC = 1. Program CLKXDIV bits to obtain the bit clock rate desired. Configure
CLKXP and CLKXM bits as desired, because CLKX is not actually used in the DIT protocol.
•
AHCLKXCTL: Program all fields according to high-frequency clock desired.
•
XTDM: Set to FFFF FFFFh for all active slots for DIT transfers.
•
XINTCTL: Program all fields according to interrupts desired.
•
XCLKCHK: Program all fields according to clock checking desired.
•
SRCTLn: Set SRMOD = 1 (transmitter) for the DIT pins. DISMOD field is don't care for DIT mode.
•
DITCSRA[n], DITCSRB[n]: Program the channel status bits as desired.
•
DITUDRA[n], DITUDRB[n]: Program the user data bits as desired.
10.2.6.3.3 DIT Channel Status and User Data Register Files
The channel status registers (DITCSRAn and DITCSRBn) and user data registers (DITUDRAn and
DITUDRBn) are not double buffered. Typically the programmer uses one of the synchronizing
interrupts, such as last slot, to create an event at a safe time so the register may be updated. In
addition, the CPU reads the transmit TDM slot counter to determine which word of the register is being
used.
It is a requirement that the software avoid writing to the word of user data and channel status that are
being used to encode the current time slot; otherwise, it will be indeterminate whether the old or new
data is used to encode the bitstream.
The DIT subframe format is defined in
Data (U) are defined in these DIT control registers:
•
DITCSRA0 to DITCSRA5: The 192 bits in these six registers contain the channel status information
for the LEFT channel within each frame.
•
DITCSRB0 to DITCSRB5: The 192 bits in these six registers contain the channel status information
for the RIGHT channel within each frame.
•
DITUDRA0 to DITUDRA5: The 192 bits in these six registers contain the user data information for
the LEFT channel within each frame.
•
DITUDRB0 to DITUDRB5: The 192 bits in these six registers contain the user data information for
the RIGHT channel within each frame.
The S/PDIF block format is shown in
frame 191). Within each frame there are two subframes (subframe 1 and 2 for left and right channels,
respectively). The channel status and user data information sent on each subframe is summarized in
Table
10-4.
1034 Multichannel Audio Serial Port (McASP)
Preliminary
Section
10.1.6.2.2. The channel status information (C) and User
Figure
10-12. There are 192 frames within a block (frame 0 to
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Advertisement
Table of Contents
