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20.3.1.2.2.3 Bulk OUT Error Handling: Peripheral Mode
If the software wants to shut down the Bulk OUT pipe, it should set the SENDSTALL bit (bit 5 of
PERI_RXCSR). When the controller receives the next packet it will send a STALL to the host, set the
SENTSTALL bit (bit 6 of PERI_RXCSR) and generate an interrupt.
When the software receives an interrupt with the SENTSTALL bit (bit 6 of PERI_RXCSR) set, it should
clear this bit. It should however leave the SENDSTALL bit set until it is ready to re-enable the Bulk OUT
pipe.
NOTE: If the host failed to receive the STALL packet for some reason, it will send another packet, so it
is advisable to leave the SENDSTALL bit set until the software is ready to re-enable the Bulk OUT pipe.
When a Bulk OUT pipe is re-enabled, the data toggle sequence should be restarted by setting the
CLRDATATOG bit (bit 7) in the PERI_RXCSR register.
20.3.1.3 Interrupt Transfer: Peripheral Mode
An Interrupt IN transaction uses the same protocol as a Bulk IN transaction and the configuration and
operation mentioned on prior sections apply to Interrupt transfer too with minor changes. Similarly, an
Interrupt OUT transaction uses almost the same protocol as a Bulk OUT transaction and can be used
the same way.
Tx endpoints in the USB controller have one feature for Interrupt IN transactions that they do not
support in Bulk IN transactions. In Interrupt IN transactions, the endpoints support continuous toggle of
the data toggle bit.
This feature is enabled by setting the FRCDATATOG bit in the PERI_TXCSR register (bit 11). When
this bit is set, the controller will consider the packet as having been successfully sent and toggle the
data bit for the endpoint, regardless of whether an ACK was received from the host.
Another difference is that interrupt endpoints do not support PING flow control. This means that the
controller should never respond with a NYET handshake, only ACK/NAK/STALL. To ensure this, the
DISNYET bit in the PERI_RXCSR register (bit 12) should be set to disable the transmission of NYET
handshakes in high-speed mode.
Though DMA can be used with an interrupt OUT endpoint, it generally offers little benefit as interrupt
endpoints are usually expected to transfer all their data in a single packet.
20.3.1.4 Isochronous Transfer: Peripheral Mode
Isochronous transfers are used when working with isochronous data. Isochronous transfers provide
periodic, continuous communication between host and device.
20.3.1.4.1 Isochronous IN Transactions: Peripheral Mode
An Isochronous IN transaction is used to transfer periodic data from the function controller to the host.
The following optional features are available for use with a Tx endpoint used in Peripheral mode for
Isochronous IN transactions:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting
transmission to the host. Double packet buffering is enabled by setting the DPB bit of TXFIFOSZ
register (bit 4).
NOTE: Double packet buffering is generally advisable for isochronous transactions in order to avoid
underrun errors as described in later section.
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint
is able to accept another packet in its FIFO. This feature allows the DMA controller to load packets
into the FIFO without processor intervention.
However, this feature is not particularly useful with Isochronous endpoints because the packets
transferred are often not maximum packet size and the PERI_TXCSR register needs to be
accessed following every packet to check for Underrun errors.
When DMA is enabled and DMAMODE bit of PERI_TXCSR is set, endpoint interrupt will not be
generated for completion of packet transfer. Endpoint interrupt will be generated only in the error
conditions.
SPRUGX9 – 15 April 2011
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Preliminary
© 2011, Texas Instruments Incorporated
Protocol Description(s)
1773
Universal Serial Bus (USB)
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