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Registers
Table 7-10. I2C Interrupt Enable Set Register (I2C_IRQENABLE_SET) Field Descriptions (continued)
Bit
Field
Value
5
GC_IE
0
1
4
XRDY_IE
0
1
3
RRDY_IE
0
1
2
ARDY_IE
0
1
1
NACK_IE
0
1
0
AL_IE
0
1
870
Inter-Integrated Circuit (I2C) Controller Module
Preliminary
Description
General call interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[GC].
General call interrupt disabled
General call interrupt enabled
Transmit data ready interrupt enable set. Mask or unmask the interrupt signaled by bit in
I2C_STAT[XRDY].
Transmit data ready interrupt disabled
Transmit data ready interrupt enabled
Receive data ready interrupt enable set. Mask or unmask the interrupt signaled by bit in
I2C_STAT[RRDY]
Receive data ready interrupt disabled
Receive data ready interrupt enabled
Register access ready interrupt enable set. Mask or unmask the interrupt signaled by bit in
I2C_STAT[ARDY].
Register access ready interrupt disabled
Register access ready interrupt enabled
No acknowledgement interrupt enable set. Mask or unmask the interrupt signaled by bit in
I2C_STAT[NACK].
Not Acknowledge interrupt disabled
Not Acknowledge interrupt enabled
Arbitration lost interrupt enable set. Mask or unmask the interrupt signaled by bit in I2C_STAT[AL].
Arbitration lost interrupt disabled
Arbitration lost interrupt enabled
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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