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Registers
Table 16-37. Port PHY Control Register (P#PHYCR) Field Descriptions (continued)
Bit
Field
15-13
RXCDR
12
RXLOS
11-10
LOOPBACK
9
RXINVPAIR
8-7
CLKBYP
1628
Serial ATA (SATA) Controller
Preliminary
Value
Description
0-7h
Receiver Clock/data Recovery. Configures the clock/data recovery algorithm.
0
First order, threshold of 1. Phase offset tracking up to +/-488ppm. Suitable for use in asynchronous
systems with low frequency offset.
1h
First order, threshold of 17. Phase offset tracking up to +/-325ppm. Suitable for use in synchronous
systems. Offers superior rejection of random jitter, but is less responsive to systematic variation
such as sinusoidal jitter.
2h
Second order, high precision, threshold of 1. Highest precision frequency offset matching but
relatively poor response to changes in frequency offset, and long lock time. Suitable for use in
systems with fixed frequency offset.
3h
Second order, high precision, threshold of 1. Highest precision frequency offset matching but
relatively poor response to changes in frequency offset, and long lock time. Suitable for use in
systems with fixed frequency offset.
4h
Second order, high precision, threshold of 1. Highest precision frequency offset matching but
relatively poor response to changes in frequency offset, and long lock time. Suitable for use in
systems with fixed frequency offset.
5h
Second order, high precision, threshold of 1. Highest precision frequency offset matching but
relatively poor response to changes in frequency offset, and long lock time. Suitable for use in
systems with fixed frequency offset.
6h
Reserved.
7h
Reserved.
Loss of Signal Detection.
Note: This must be enabled by software before initialization is started on the device.
Note: Refer to PHY CFGR2 Register for what value is actually programmed into the SERDES. In
most cases, only the default will have to be used.
0
Disabled.
1
Enabled.
Transmitter and Receiver Loopback Selection.
0
Transmitter – Disabled
Receiver – Disabled
1h
Transmitter – Reserved
Receiver – Reserved
2h
Transmitter – Loopback, TX Driver Disabled. The loopback path covers all the stages of the
transmitter except the TX output itself. A differential current is passed to the receiver. The
magnitude of this current is dependent on SWING. The transmitter driver itself is disabled.
Receiver – Reserved (N/A)
3h
Transmitter – Loopback, TX Driver Enabled. As above, but the transmit driver operates normally.
Receiver – Loopback. The differential current from the transmitter is converted to a voltage and
applied to the receiver input if LOS is disabled, or to the Loss of Signal detector if LOS is enabled.
0
Receiver Invert Polarity. Inverts the polarity of RXP# and RXN#.
Clock Bypass. Facilitates bypassing of the PLL with either REFCLKP/N or TESTCLKT, and
bypassing of the recovered receiver clock with TESTCLKR.
Note: This field applies to Port 0 only, P0PHYCR. This bit is reserved for Port 1, P1PHYCR.
0
No bypass. Macro operates normally from the PLL.
1h
Reserved.
2h
Functional Bypass. The macro operates functionally at low speed using TESTCLKT and
TESTCLKR.
3h
REFCLK Observe. The PLL is bypassed by REFCLKP/N. This diagnostic capability is designed to
facilitate observation of the reference clock from macros containing transmitters
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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