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Architecture
The OCP clock domain synchronous registers TIDR, TIOCP_CFG, TISTAT,
IRQ_EOI,IRQSTATUS,IRQSTATUS_RAW, IRQENABLE_SET, IRQENABLE_CLR, IRQWAKEEN,
TWPS and TSICR are not affected by the posted/non-posted mode selection; the write/read operation
is effective and acknowledged (command accepted) after one OCP clock cycle from the command
assertion.
The configuration posted/non-posted is made by setting the PIFREQRATIO when the module is
integrated. The PIFREQRATIO signal should be tied to '1' when the freq (timer) < freq (OCP)/4
frequency, and tied to 0 when it is the opposite frequency ratio. The PIFREQRATIO represent the reset
value of the TSICR (POSTED bit). The configuration can be changed (overwritten) by software, writing
the TSICR (POSTED bit) register.
The following cases are possible:
•
Posted Mode can be used when the functional frequency range is: freq (timer) < freq (OCP)/4.
•
Non-Posted Mode can be used regardless of the frequency range. Recommended frequency is: freq
(timer) >= freq (OCP)/4.
NOTE: The Non-Posted Mode can be also used when freq (timer) < freq (OCP)/4, but it is
recommended to use the Posted Mode. Using Non-Posted Mode will delay the command
accept and the transaction latency will be as described in the below chapters. Posted
mode offers an OCP interface latency improvement and can be used only if the
frequencies respect the freq (timer) < freq (OCP)/4 formula.
17.2.4 Write Registers Access
17.2.4.1 Write Posted
This mode can be used only if the functional frequency range is freq (timer) < freq (OCP)/4.
This mode is used if TSICR (POSTED bit) is set to 1 in the timer control register.
This mode uses a posted-write scheme to update any internal register. The write transaction is
immediately acknowledged on the OCP interface, although the effective write operation will occur later,
due to a resynchronisation in the timer clock domain. This has the advantage of not stalling either the
interconnect system, or the CPU that requested the write transaction. For each register, a status bit is
provided, that is set if there is a pending write access to this register.
In this mode, it is mandatory that the CPU checks the status bit prior to any write access. In case a
write is attempted to a register with a previous access pending, the previous access is discarded
without notice (this can lead to unexpected results also).
There is one status bit per register, accessible in the Timer Write Posted Status Register. When the
timer module operates in this mode, there is an automatic sampling of the current timer counter value,
in an OCP-synchronized capture register. Consequently, any read access to the timer counter register
does not add any re-synchronization latency; the current value is always available.
A register read following a write posted register (on the same register) is not insured to read the
previous write value if the write posted process is not completed. Software synchronization should be
used to avoid non-coherent read.
The drawback of this automatic update mechanism is that it assumes a given relationship between the
OCP interface frequency and the timer functional frequency.
This posted period is defined as the interval between the posted write access request and the reset of
the posted bit in TWPS register, and can be quantified:
T (reset posted max.) = 3 OCP clock + 2.5 TIMER clock
The time when the write accomplishes is:
T (write accomplish) = 1 OCP clock + 2.5 TIMER clock
1642
Timers
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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