Table of Contents
Advertisement
Protocol Description(s)
20.3.2.2 Bulk Transfer: Host Mode
Bulk transactions are handled by endpoints other than endpoint 0. It is used to handle non-periodic,
large bursty communication typically used for a transfer that use any available bandwidth and can also
be delayed until bandwidth is available.
20.3.2.2.1 Bulk IN Transactions: Host Mode
A Bulk IN transaction may be used to transfer non-periodic data from the external USB peripheral to the
host.
The following optional features are available for use with an Rx endpoint used in host mode to receive
the data:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception
from the host. This allows that one packet can be received while another is being read. Double
packet buffering is enabled by setting the DPB bit of RXFIFOSZ register (bit 4).
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint
has a packet in its FIFO. This feature can be used to allow the DMA controller to unload packets
from the FIFO without processor intervention.
When DMA is enabled, endpoint interrupt will not be generated for completion of packet reception.
Endpoint interrupt will be generated only in the error conditions. For more information see section on
CPPI DMA
20.3.2.2.1.1 Bulk IN Setup: Host Mode
Before initiating any Bulk IN Transactions in Host mode:
•
The HOST_RXTYPE register for the endpoint that is to be used needs to be programmed as:
– Operating speed in the SPEED bit field (bits 7 and 6).
– Set 10 (binary value) in the PROT field for bulk transfer.
– Endpoint Number of the target device in RENDPN field. This is the endpoint number contained in
the Rx endpoint descriptor returned by the target device during enumeration.
•
The RXMAXP register for the controller endpoint must be written with the maximum packet size (in
bytes) for the transfer. This value should be the same as the wMaxPacketSize field of the Standard
Endpoint Descriptor for the target endpoint.
•
The HOST_RXINTERVAL register needs to be written with the required value for the NAK limit
(2-215 frames/microframes), or set to zero if the NAK timeout feature is not required.
•
The relevant interrupt enable bit in the INTRRXE register should be set (if an interrupt is required for
this endpoint).
Note: Whether interrupt is handled from PDR level or Core level, interrupt is required to be enabled
at the core level. See details on Core Interrupt registers, CTRLR register, and sections on Interrupt
Handling
•
The AUTOREQ bit field should be used only when servicing transfers using CPU mode and must be
cleared when using DMA Mode. For DMA Mode, dedicated registers USB0/1 Req Registers exist
and the HOST_RXCSR[AUTOREQ] should be cleared.
When DMA is enabled, the following bits of HOST_RXCSR register should be set as:
– Clear AUTOCLEAR.
– Set DMAEN (bit 13) to 1 if a DMA request is required for this endpoint.
– Clear DSINYET (bit 12) to 0 to allow normal PING flow control. This will affect only High Speed
transactions.
– Clear DMAMODE (bit 11) to 0.
Note: If DMA is enabled, the USB0/1 Auto Req register can be set for generating IN tokens
automatically after receiving the data. Set the bit field RXn_AUTOREQ (where n is the endpoint
number) with binary value 01 or 11.
1788
Universal Serial Bus (USB)
Preliminary
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
Submit Documentation Feedback
Advertisement
Table of Contents
