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Architecture
Event Flag
Event Mask
SD_STAT[21] DCRC
SD_IE[21]
DCRC_ENABLE
SD_STAT[20] DTO
SD_IE[20]
DTO_ENABLE
SD_STAT[19] CIE
SD_IE[19]
CIE_ENABLE
SD_STAT[18] CEB
SD_IE[18]
CEB_ENABLE
SD_STAT[17] CCRC
SD_IE[17]
CCRC_ENABLE
SD_STAT[16] CTO
SD_IE[16]
CTO_ENABLE
SD_STAT[15] ERRI
SD_IE[15]
ERRI_ENABLE
SD_STAT[10] BSR
SD_IE[10]
BSR_ENABLE
SD_STAT[8] CIRQ
SD_IE[8]
CIRQ_ENABLE
SD_STAT[5] BRR
SD_IE[5]
BRR_ENABLE
SD_STAT[4] BWR
SD_IE[4]
BWR_ENABLE
SD_STAT[3] DMA
SD_IE[3]
DMA_ENABLE
SD_STAT[2] BGE
SD_IE[2]
BGE_ENABLE
SD_STAT[1] TC
SD_IE[1]
TC_ENABLE
SD_STAT[0] CC
SD_IE[0]
CC_ENABLE
938
Secure Digital (SD)/—Secure Digital I/O (SDIO) Card Interface
Preliminary
Table 9-5. Events (continued)
Map To
Description
IRQ
Data CRC error. This bit is set automatically when there is a CRC16 error in
the data phase response following a block read command or if there is a
3-bit CRC status different of a position "010" token during a block write
command.
IRQ
Data Timeout error. This bit is set automatically according to the following
conidtions: A) busy timeout for R1b, R5b response. B) busty timeout after
write CRC status. C) write CRC status timeout, or D) read data timeout.
IRQ
Command Index Error. This bit is set automatically when response index
differs from corresponding command index previously emitted. The check is
enabled through SD_CMD[20] CICE bit.
IRQ
Command End Bit error. This bit is set automatically when detecting a 0 at
the end bit position of a command response.
IRQ
Command CRC error. This bit is set automatically when there is a CRC7
error in the command response. CRC check is enabled through the
SD_CMD[19] CCCE bit.
IRQ
Command Timeout error. This bit is set automatically when no response is
received within 64 clock cycles from the end bit of the command. For
commands the reply within 5 clock cycles, the timeout is still detected at 64
clock cycles.
IRQ
Error Interrupt. If any of the bits in the Error Interrupt Status register
(SD_STAT[24:15]) are set, the this bit is set to 1.
IRQ
Boot Status Receieved interrupt. This bit is set automatically when
SD_CON[18] BOOT_CF0 is set to 1 or 2h and boot status is received on
the dat0 line. This interrupt is only used for MMC cards.
IRQ
Card Interrupt. This bit is only used for SD, SDIO, and CE-ATA cards. In
1-bit mode, interrupt source is asynchronous (can be a source of
asynchronous wake-up). In 4-bit mode, interrupt source is sampled during
the interrupt cycle. In CE-ATA mode, interrupt source is detected when the
card drive CMD line to zero during one cycle after data transmission end.
IRQ
Buffer Read ready. This bit is set automatically during a read operation to
the card when one block specified by SD_BLK[10:0] BLEN is completely
written in the buffer. It indicates that the memory card has filled out the
buffger and the local host needs to empty the buffer by reading it.
IRQ
Buffer Write ready. This bit is automatically set during a write operation to
the card when the host can write a complete block as specified by
SD_BLK[10:0] BLEN. It indicates that the memory card has emptied one
block from the bugger and the local host is able to write one block of data
into the buffer.
IRQ
DMA interrupt. This status is set when an interrupt is required in the AMDA
instruction and after the data transfer is complete.
IRQ
Block Gap event. When a stop at block gap is requested (SD_HCTL[16]
SBGR), this bit is automatically set when transaction is stopped at the block
gap during a read or write operation.
IRQ
Transfer completed. This bit is always set when a read/write transfer is
completed or between two blocks when the transfer is stopped due to a
stop at block gap requesd (SD_HCTL[16 SBGR). In read mode this bit is
automatically set on completion of a read transfer (SD_PSTATE[9] RTA). In
write mode, this bit is automatically set on completion of the DAT line use
(SD_PSTATE[2] DLA).
IRQ
Command complete. This bit is set when a 1-to-0 transition occurs in the
register command inhibit (SD_PSTATE[0] CMDI). If the command is a type
for which no response is expected, then the command complete interrupt is
generated at the end of the command. A command timeout error
(SD_STAT[16] CTO) has higher priority than command complete
(SD_STAT[0] CC). If a response is expected but none is received, the a
Command Timeout error is detected and signaled instead of the Command
Complete interrupt.
© 2011, Texas Instruments Incorporated
www.ti.com
SPRUGX9 – 15 April 2011
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