Timer Control Status Register (Tcsr) - Fujitsu MB90460 Series Hardware Manual

CHAPTER 15 MULTI-PULSE GENERATOR
15.4.7

Timer Control Status Register (TCSR)

The Timer Control Status Register (TCSR) is used to control the operation of the 16-bit
timer.
■ Timer Control Status Register (TCSR)
Address bit 7
TCLR
00008E MODE
H
R/W
X : Indeterminate
R/W : Readable and writable
: Initial value
— : Not used
390
Figure 15.4-12 Timer Control Status Register (TCSR)
6 5 4 3
ICLR ICRE TMEN
R/W R/W R/W R/W
CLK2 CLK1 CLK0
0
0
0
0
1
1
1
1
φ: Machine cycle
TMEN
ICRE
ICLR
MODE
TCLR
2 1 0 Initial value
CLK2 CLK1 CLK0 00000000
R/W R/W R/W
Clock frequency selection bit
Count
φ = 16 MHz
clock
φ
0 0
φ/2
0 1
φ/4
1 0
φ/8
1 1
φ/16
0 0
φ/32
0 1
φ/64
1 0
φ/128
1 1
0 Counting is disabled. (Initial value)
1 Counting is enabled.
Compare clear interrupt request enable bit
0 Interrupt is disabled.
1 Interrupt is enabled.
Compare clear interrupt request flag bit
Read
0 No interrupt request.
1 Has interrupt request.
Counter reset condition bit
0 Reset counter by write timing trigger.
1 Reset counter by position detection trigger.
Read
0
Always read as "0".
1
B
φ = 8 MHz φ = 4 MHz
0.25 µs
62.5 ns 125 ns
0.25 µs 0.5 µs
125 ns
0.25 µs 0.5 µs 1 µs
0.5 µs 1 µs 2 µs
1 µs 2 µs 4 µs
2 µs 4 µs 8 µs
4 µs 8 µs 16 µs
8 µs 16 µs 32 µs
Timer enable bit
Write
Clear this bit.
No effect.
Timer clear bit
Write
No effect.
Initialize counter to "0000
φ = 1 MHz
1 µs
2 µs
4 µs
8 µs
16 µs
32 µs
64 µs
128 µs
".
H