Communication Prescaler Control Register (Cdcr) - Fujitsu MB90460 Series Hardware Manual

CHAPTER 17 UART
17.4.5

Communication Prescaler Control Register (CDCR)

This register controls the division of machine clocks.
■ Communication Prescaler Control Register (CDCR)
The operation clocks of UART can be obtained by dividing machine clocks. UART is designed to obtain
certain baud rates for various machine cycles. Output from the communication prescaler is used for the
operation clocks of I/O extended serial interfaces. The CDCR bit configuration is shown below.
Address bit 15
000019
H
MD
00001B
H
R/W
X : Indeterminate
R/W : Read and write
: Initial value
— : Not used
484
Figure 17.4-7 Communication Prescaler Control Register
14 13 12 11
— — — —
— — — —
MD
0
1
1
1
1
1
1
1
1
MD
10 9 8
DIV2 DIV1 DIV0
R/W R/W R/W
DIV2 DIV1 DIV0
— — —
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Machine clock divide mode select
0
Stops the communication prescaler.
1
Operates the communication prescaler.
Initial value
0XXXX000
B
div
Setting not allowed
1
2
3
4
5
6
7
8