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14.6.4.2
Operation in Dead-time Timer Mode
The dead-time generator will input the real-time output (RT1/RT3/RT5), select PPG timer
0 pulse output, and output non-overlap signals (inverted signals) to external pins (RTO0
to RTO5).
■ Making Non-overlap Signals by using RT1/RT3/RT5 in Normal Polarity
(DTCR0/DTCR1/DTCR2:TMD2 to TMD0=100
When selecting non-overlap signal for an active level "0" (normal polarity) in DTCR0/DTCR1/
DTCR2:DMOD, a delay corresponding to the non-overlap time set in the TMRR0/TMRR1/TMRR2
register (16-bit timer register) is applied. The delay is applied at a rising edge of RT1/RT3/RT5 or its
falling edge. If RT1/RT3/RT5 pulse width is smaller than the set non-overlap time, the 16-bit timer will
restart down-counting from TMRR0/TMRR1/TMRR2 value at the next RT's edge.
Figure 14.6-25 Non-overlap Signal Generation by RT1/RT3/RT5 in Normal Polarity
Setting up registers:
• TCDT
• TCCS
• OCCP0 to OCCP5 : XXXX
• TMRR0 to TMRR2 : XXXX
• SIGCR
Note:
"X" must be set according to the operation.
16-bit timer 0
Count
value
RT1
RTO0 (U)
RTO1 (X)
: 0000
H
: X--XXXXXX0X0XXX
(Compare value)
H
(Non-overlap timing setting)
H
: XXXXXXXX
(DTTI0 input and 16-bit timer count clock setting)
B
1 machine cycle
Pin name
RTO0 (U)
Signal with delay is applied at RT1 rising edge
RTO2 (V)
Signal with delay is applied at RT3 rising edge
RTO4 (W)
Signal with delay is applied at RT5 rising edge
RTO1 (X)
Inverted signal with delay is applied at RT1 falling edge
RTO3 (Y)
Inverted signal with delay is applied at RT3 falling edge
RTO5 (Z)
Inverted signal with delay is applied at RT5 falling edge
CHAPTER 14 MULTI-FUNCTIONAL TIMER
)
B
• CPCLR
• OCS0 to OCS5
B
• DTCR0 to DTCR2 : 0XXXX100
1.5 machine cycle
Output signal
: XXXX
(Cycle setting)
H
: -XX1XXXXXXXXXX11
B
B
TMRR0 set value
343
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