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Position Detect Timing Interrupt
If the PDIE bit of the Output Control Register (OPCR: PDIE) is set to "1", this Position Detect Interrupt is
generated when the write timing is output by Position Detect Circuit to make data transfer from one of 12
Output Data Buffer Registers (OPDBRB to OPDBR0) to the Output Data Register (OPDR). This write
timing output can be generated by either the compare match of the level of the position input (SNI2 to
SNI0) with RDA2 to RDA0 bits of the Output Data Register (OPDR: RDA2 to RDA0), or a edge detected
of the position input (SNI2 to SNI0) with one of 3 different kinds of edge setting.
When this interrupt is generated, the position detect interrupt flag bit of the Output Control Register
(OPCR: PDIF) is set to "1".
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Compare Match Interrupt
If the CPIE bit of the Input Control Register (IPCR: CPIE) is set to "1", this Compare Match Interrupt is
generated when the RDA2 to RDA0 bits of the Output Data Register (OPDR: RDA2 to RDA0) are
matched with the CPD2 to CPD0 bits of the Input Control Register (IPCR: CPD2 to CPD0).
When this interrupt is generated, the Compare match interrupt flag bit of the Input Control Register (IPCR:
CPIF) is set to "1".
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DTTI1 Interrupt
If the DTIE bit of the Output Control Register (OPCR: DTIE) is set to "1", this DTTI1 Interrupt is
generated whenever a low input is detected at the DTTI1 pin.
When this interrupt is generated, the DTTI1 interrupt flag bit of the Output Control Register (OPCR: DTIF)
is set to "1".
■ Multi-pulse Generator Interrupt Source
INTERRUPT #22:This interrupt is generated when a DTTI1 interrupt is happened.
INTERRUPT #26:This interrupt is generated when either a Write Timing interrupt or Compare
INTERRUPT #28:This interrupt is generated when either a Position Detect interrupt or Compare
DTTI1 interrupt is generated if OPCR: DTIE is set to "1" when a low level input
is detected at the DTTI1 pin.
Clear interrupt is happened.
Write timing interrupt is generated if OPCR: WTIE is set to "1" when a write timing
signal is generated from the Data Write Control Circuit.
Compare clear interrupt is generated if TCSR: ICRE is set to "1" when the count value of
16-bit timer matches with the Compare clear register (CPCR).
Match interrupt is happened.
Position detect interrupt is generated if OPCR: PDIE is set to "1" when an effective edge
at SNI2 to SNI0 is detected.
Compare match interrupt is generated if IPCR: CPIE is set to "1" when the SNI2 to SNI0
inputs match with the RDA2 to RDA0 bits of the Output Data Register (OPDR).
CHAPTER 15 MULTI-PULSE GENERATOR
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