Fujitsu MB90460 Series Hardware Manual page 323

CHAPTER 14 MULTI-FUNCTIONAL TIMER
Table 14.4-4 Compare Control Register (OCS0/OCS2/OCS4)
Bit name
IOP1:
bit7 Compare match
interrupt flag bit
IOP0:
bit6 Compare match
interrupt flag bit
IOE1:
bit5 Compare match
interrupt enable bit
IOE0:
bit4 Compare match
interrupt enable bit
BUF1:
bit3 Compare buffer
disable bit
BUF0:
bit2 Compare buffer
disable bit
CST1:
bit1 Compare operation
enable bit
CST0:
bit0 Compare operation
enable bit
304
• This bit is an interrupt flag for when compare register 1/3/5 is matched with the value of
16-bit free-run timer.
• "1" is set to this bit when the compare register value matches the 16-bit free-run timer
value.
• While the interrupt request bits (IOE1) is enabled, an output compare interrupt occurs
when the IOP1 bit is set.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
• This bit is an interrupt flag for when compare register 0/2/4 is matched with the value of
16-bit free-run timer.
• "1" is set to this bit when the compare register value matches the 16-bit free-run timer
value.
• While the interrupt request bits (IOE0) is enabled, an output compare interrupt occurs
when the IOP0 bit is set.
• Writing "0" will clear this bit.
• Writing "1" has no effect.
• In read-modify-write operation, "1" is always read.
• This bit is used to enable output compare interrupt for compare register 1/3/5.
• While the "1" is written to this bit, an output compare interrupt occurs when an interrupt
flag (IOP1) is set.
• This bit is used to enable output compare interrupt for compare register 0/2/4.
• While the "1" is written to this bit, an output compare interrupt occurs when an interrupt
flag (IOP0) is set.
• This bit is used to disable buffer function for output compare register 1/3/5.
• Writing "0" will enable the buffer function.
• This bit is used to disable buffer function for output compare register 0/2/4.
• Writing "0" will enable the buffer function.
• This bit is used to enable the compare operation between 16-bit free-run timer and
compare register 1/3/5.
• Ensure that a value is written into the compare register and timer data register before the
compare operation is enabled.
Note:
Since output compare is synchronized with the 16-bit free-run timer clock, stopping the
16-bit free-run timer stops compare operation.
• This bit is used to enable the compare operation between 16-bit free-run timer and
compare register 0/2/4.
• Ensure that a value is written into the compare register and timer data register before the
compare operation is enabled.
(Note)
Since output compare is synchronized with the 16-bit free-run timer clock, stopping the
16-bit free-run timer stops compare operation.
Function