Compare Control Registers (Ocs0 To Ocs5) - Fujitsu MB90460 Series Hardware Manual

14.4.5

Compare Control Registers (OCS0 to OCS5)

Compare control register is used to control the output level, output enable, output
reverse mode, compare operation enable, compare match interrupt enable and compare
match interrupt flag for RTO0 to RTO5.
■ Compare Control Register, Upper Byte (OCS1/OCS3/OCS5)
Address bit15
ch.1: 00007D
H
ch.3: 00007F
H
ch.5: 000081
H
R/W : Read and write
: Initial value
— : Not used
Figure 14.4-12 Compare Control Register (OCS1/OCS3/OCS5)
14 13 12
—
BTS1 BTS0 CMOD OTE1 OTE0 OTD1 OTD0 -1100000
— R/W R/W R/W
OTD0
0
1
OTD1
0
1
OTE0
0
1
OTE1
0
1
CMOD
RT0/RT2/RT4: The level is reversed upon a match with compare register 0/2/4
0
RT1/RT3/RT5: The level is reversed upon a match with compare register 1/3/5 respectively
RT0/RT2/RT4: The level is reversed upon a match with compare register 0/2/4
1
RT1/RT3/RT5: The level is reversed upon a match with compare register (0or1)/(2or3)/(4or5)
BTS0
0
1
BTS1
0
1
CHAPTER 14 MULTI-FUNCTIONAL TIMER
11 10 9 8
R/W R/W R/W R/W
Output level bit
Write
Output "0" for RT0/RT2/RT4
Output "1" for RT0/RT2/RT4
Output level bit
Write
Output "0" for RT1/RT3/RT5
Output "1" for RT1/RT3/RT5
Output enable bit
General-purpose port (P30/P32/P34)
Output compare output pin (RTO0/RTO2/RTO4)
Output enable bit
General-purpose port (P31/P33/P35)
Output compare output pin (RTO1/RTO3/RTO5)
Output level reverse mode bit
Buffer transfer select bit
Transfer at zero detect ( channel 0/2/4)
Transfer at compare clear match (channel 0/2/4)
Buffer transfer select bit
Transfer at zero detect (channel 1/3/5)
Transfer at compare clear match (channel 1/3/5)
Initial value
B
Read
Current output value of RT0/
RT2/RT4
Read
Current output value of RT1/
RT3/RT5
301