Table of Contents
Advertisement
■ Operation of the Time-base Timer
The following operations are shown in Figure 10.6-1:
• A power-on reset occurs.
• Sleep mode is entered during operation of the interval timer function.
• A counter clear request is issued.
When stop mode is entered, the time-base timer is cleared and its operation stops. On return from stop
mode, the time-base timer counts the oscillation stabilization time.
Counter value
Oscillation stabilization
delay overflow
TBOF bit
TBIE bit
SLP bit
(STBC register)
STP bit
(STBC register)
When 11
has been set in the interval selection bit
B
(TBTC:TBC1,TBC0) of the time-base timer control register
: Indicates the oscillation stabilization time.
Figure 10.6-1 Time-base Timer Operations
3FFFF
H
0000
H
CPU operation starts
Power-on reset
(optional)
Cleared by the interrupt
Releasing of interval interrupt sleep
Cleared by transition to
stop mode.
Interval cycle
(TBTC: TBC1, TBC0 = 11
)
B
handling
routine.
Sleep mode
Stop
Releasing of Stop by an external interrupt
CHAPTER 10 TIME-BASE TIMER
Counter clear
(TBTC: TBR = 0)
215
Advertisement
Table of Contents
