Fujitsu MB90460 Series Hardware Manual page 393

CHAPTER 15 MULTI-PULSE GENERATOR
■ Output Control Lower Register (OPCLR)
Address bit 7
PDIF
00008A
H
R/W
X : Indeterminate
R/W : Readable and writable
: Initial value
— : Not used
374
Figure 15.4-3 Output Control Lower Register (OPCLR)
6 5 4 3
PDIE OPE5 OPE4 OPE3
R/W R/W R/W R/W
2 1 0 Initial value
OPE2 OPE1 OPE0 00000000
R/W R/W R/W
OPE0 OPT0 output enable bit
0 Disable OPT0 pin output. (Initial value)
1 Enable OPT0 pin output.
OPE1 OPT1 output enable bit
0 Disable OPT1 pin output. (Initial value)
1 Enable OPT1 pin output.
OPE2 OPT2 output enable bit
0 Disable OPT2 pin output. (Initial value)
1 Enable OPT2 pin output.
OPE3 OPT3 output enable bit
0 Disable OPT3 pin output. (Initial value)
1 Enable OPT3 pin output.
OPE4 OPT4 output enable bit
0 Disable OPT4 pin output. (Initial value)
1 Enable OPT4 pin output.
OPE5 OPT5 output enable bit
0 Disable OPT5 pin output. (Initial value)
1 Enable OPT5 pin output.
PDIE Position detection interrupt enable bit
0 Disable interrupt. (Initial value)
1
Position detection interrupt request flag bit
PDIF
Read
0 No valid detected.
1 Valid detected.
B
Enable interrupt.
Write
Clear this bit.
No effect.