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Table 17.4-4 Communication Prescaler Control Register
Bit name
MD:
bit15
Machine clock divide mode select bit
bit14
to
Reserved bits
bit12
bit10
DIV2 to DIV0:
to
Machine clock division bits
bit8
• This bit is the operation enable bit of the communication prescaler.
• When "0" is set, the communication prescaler stops.
• When "1" is set, the communication prescaler operates.
• Always read as "0".
• These bits determines the machine clock division ratios.
• Division ratios can only be set when MD is "1".
(Note)
If division ratio is changed, wait 2 cycles as stabilization time
before starting communication.
CHAPTER 17 UART
Function
485
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