Fujitsu MB90460 Series Hardware Manual page 360

■ Generating GATE Signal from Rising Edge of Each RTx until 16-bit Timer 0/1/2
Underflow when GTENx is active (DTCR0/DTCR1/DTCR2:TMD2 to TMD0=010
Figure 14.6-23 Generating GATE Signal from Rising Edge of RTx until 16-bit Timer Underflow
16-bit free-run timer
FFFF
BFFF
Count value
7FFF
3FFF
0000
Compare register 0
value
Compare register 1
value
RT0
RT1
GATE0
GATE1
GATE
Note:
Each 16-bit timer is used for two RTs. i.e. 16-bit timer 0 is used for RT0 and RT1; 16-bit timer 1 is
used for RT2 and RT3; 16-bit timer 2 is used for RT4 and RT5. Therefore, do not use an RT and
attempt to start the corresponding timer that is already operating. Doing so may cause that the
outputting GATE signal will be extended and malfunction will be occurred.
H
H
H
H
H
BFFF
H
7FFF
H
CHAPTER 14 MULTI-FUNCTIONAL TIMER
Time of
Time of
16-bit timer 0
16-bit timer 0
)
B
Time
341