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12.5
16-Bit Reload Timer Interrupts
The 16-bit reload timer is enabled to generate an interrupt request in an underflow of
the counter. It is also coordinated with the extended intelligent I/O service (EI
■ 16-bit Reload Timer Interrupts
Table 12.5-1 lists the interrupt control bits and interrupt causes of the 16-bit reload timer.
Table 12.5-1 Interrupt Control Bits and Interrupt Causes of the 16-bit Reload Timer
Interrupt request flag bit
Interrupt request enable bit TMCSRL0: INTE
Interrupt cause
In the 16-bit reload timer, the UF bit of the timer control status register (TMCSRL0/TMCSRL1) is set to
"1" by an underflow (from 0000
(TMCSRL0/TMCSRL1:INTE = 1) in this operation, the interrupt request is output to the interrupt
controller.
■ 16-bit Reload Timer Interrupts and EI
Table 12.5-2 lists the 16-bit reload timer interrupts and EI
Table 12.5-2 16-bit Reload Timer Interrupts and EI
Channel
*1
16-bit reload timer 0
*2
16-bit reload timer 1
*1: The same interrupt number as that for waveform sequencer 16-bit timer counter borrow is assigned to 16-bit reload timer 0.
*2: The same interrupt number as that for output compare ch 2 match is assigned to 16-bit reload timer 1.
2
■ EI
OS Function of the 16-bit Reload Timer
Since the 16-bit reload timer has a circuit that coordinates with EI
underflow occurs.
However, EI
(ICR) do not use interrupts. For example, when 16-bit reload timer 0 uses EI
waveform generator 16-bit timer 0/1/2 counter borrow must be disabled.
16-bit reload timer 0
TMCSRL0: UF
Underflow of the 16-bit down counter (TMR0) Underflow of the 16-bit down counter (TMR1)
H
Interrupt control register
Interrupt
number
Register name
#30 (1E
)
ICR09
H
#18 (12
)
ICR03
H
2
OS is available only when other peripheral functions sharing the interrupt control register
TMCSRL1: UF
TMCSRL1: INTE
to FFFF
) of the down counter. If an interrupt request is enabled
H
2
OS
2
OS.
2
OS
Address
Lower
0000B9
FFFF84
H
0000B3
FFFFB4
H
CHAPTER 12 16-BIT RELOAD TIMER
16-bit reload timer 1
Vector table address
Middle
Upper
FFFF85
FFFF86
H
H
FFFFB5
FFFFB6
H
H
2
OS, the counter can start EI
2
OS, interrupts of the
2
OS).
2
EI
OS
H
O
H
2
OS when an
243
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