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CHAPTER 17 UART
17.2
Block Diagram of UART
UART consists of the following 11 blocks, the block diagram is shown in Figure 17.2-1.
■ Block Diagram of UART
From
communication
prescaler
16-bit reload timer
P42/SCK0
External clock
<P62/SCK1>
P40/SIN0
<P60/SIN1>
SMR0/SMR1
register
*: Interrupt number
470
Figure 17.2-1 Block Diagram of UART
Baud rate
generator
Clock
selection
circuit
Reception status
judgment circuit
2
EI
OS reception error
signal (to CPU)
MD1
MD0
CS2
SCR0/SCR1
CS1
register
CS0
RST
SCKE
SOE
Transmission clock
Reception clock
Reception control
circuit
Start bit detect
circuit
Reception bit
counter
Reception parity
counter
Reception shifter
SIDR0/SIDR1
2
F
MC-16LX bus
PEN
P
SBL
CL
A/D
REC
RXE
TXE
Reception interrupt
#39 (27
)*
H
<#37 (25
)*>
H
Transmission
interrupt
#40 (28
)*
H
<#38 (26
)*>
H
Transmission control
circuit
Transmission
start circuit
Transmission bit
counter
Transmission
parity counter
P41/SOT0
<P61/SOT1>
Transmission shifter
SODR0/SODR1
PE
ORE
FRE
SSR0/SSR1
RDRF
register
TDRE
BDS
RIE
TIE
Control signal
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