Usage Notes On Low Power Consumption Mode - Fujitsu MB90460 Series Hardware Manual

CHAPTER 6 LOW POWER CONSUMPTION MODE
6.8

Usage Notes on Low Power Consumption Mode

Note the following six items to use low power consumption mode:
• Switching to standby mode and interrupts
• Release of standby mode by an interrupt
• Setting of standby mode
• Release of stop mode
• Release of time-base timer mode
• Oscillation stabilization wait time
■ Notes on Standby Mode
●
Switching to standby mode and interrupts
During an interrupt request to the CPU from a peripheral function, the CPU ignores the STP and SLP bits
of the low power consumption mode control register (LPMCR) even though 1 has been written to these
bits. Thus, switching to any standby mode is disabled (even after processing the interrupt is completed,
there is no switch to standby mode). If the interrupt level is higher than 7, this action does not depend on
whether the interrupt request is accepted by the CPU.
However, during execution of interrupt processing by the CPU, if the interrupt request flag for the interrupt
is cleared and no other interrupt requests have been issued, switching to standby mode can be done.
●
Release of standby mode caused by an interrupt
If an interrupt request higher than level 7 is issued from a peripheral function during the sleep, time-base
timer, or stop modes, the standby mode is released. This action does not depend on whether the CPU
accepts that interrupt.
After the release of standby mode, normal interrupt processing is performed. The CPU branches to the
interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt level
setting bits (IL2, IL1 and IL0 of ICR) is higher than the interrupt level mask register (ILM); and the
interrupt enable flag (I) of the condition code register (CCR) is set to "1" (enabled). If the interrupt is not
accepted, the CPU starts the execution with the instruction that follows the instruction in which switching
to standby mode was specified.
When interrupt processing is executed normally, the CPU first executes the instruction that follows the
instruction in which switching to standby mode was specified. The CPU then proceeds to interrupt
processing. Depending on the condition when switching to standby mode was performed, however, the
CPU may proceed to interrupt processing before executing the next instruction.
If the CPU should not branch to the interrupt processing routine immediately on return to normal mode
from standby mode, action must be taken to disable interrupts before standby mode is set.
●
Setting of standby mode
When "1" is written to the STP bit and SLP bit of LPMCR at the same time, switching to standby mode is
performed. If the MCS bit of the clock selection register (CKSCR) is "0", switching to time-base timer
mode is performed; if this bit is "1", switching to stop mode is performed.
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