Fujitsu MB90460 Series Hardware Manual page 12

F2mc-16lx 16-bit microcontroller
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MODE SETTING ....................................................................................... 157
8.1
Mode Setting ................................................................................................................................... 158
8.2
Mode Pins (MD2 to MD0) ............................................................................................................... 159
8.3
Mode Data ...................................................................................................................................... 160
I/O PORT .................................................................................................. 163
9.1
Overview of I/O Port ....................................................................................................................... 164
9.2
Registers of I/O Port ....................................................................................................................... 166
9.3
Port 0 .............................................................................................................................................. 167
9.3.1
Port 0 Registers (PDR0, DDR0 and RDR0) .............................................................................. 169
9.3.2
Operation of Port 0 .................................................................................................................... 171
9.4
Port 1 .............................................................................................................................................. 173
9.4.1
Port 1 Registers (PDR1, DDR1 and RDR1) .............................................................................. 175
9.4.2
Operation of Port 1 .................................................................................................................... 176
9.5
Port 2 .............................................................................................................................................. 178
9.5.1
Port 2 Registers (PDR2 and DDR2) .......................................................................................... 180
9.5.2
Operation of Port 2 .................................................................................................................... 181
9.6
Port 3 .............................................................................................................................................. 183
9.6.1
Port 3 Registers (PDR3 and DDR3) .......................................................................................... 185
9.6.2
Operation of Port 3 .................................................................................................................... 186
9.7
Port 4 .............................................................................................................................................. 188
9.7.1
Port 4 Registers (PDR4 and DDR4) .......................................................................................... 190
9.7.2
Operation of Port 4 .................................................................................................................... 191
9.8
Port 5 .............................................................................................................................................. 193
9.8.1
Port 5 Registers (PDR5, DDR5 and ADER) .............................................................................. 195
9.8.2
Operation of Port 5 .................................................................................................................... 196
9.9
Port 6 .............................................................................................................................................. 198
9.9.1
Port 6 Registers (PDR6 and DDR6) .......................................................................................... 200
9.9.2
Operation of Port 6 .................................................................................................................... 201
9.10
Sample I/O Port Program ............................................................................................................... 203
CHAPTER 10 TIME-BASE TIMER .................................................................................. 205
10.1
Overview of the Time-base Timer ................................................................................................... 206
10.2
Configuration of the Time-base Timer ............................................................................................ 208
10.3
Time-base Timer Control Register (TBTC) ..................................................................................... 209
10.4
Time-base Timer Interrupts ............................................................................................................ 211
10.5
Operation of the Time-base Timer .................................................................................................. 212
10.6
Usage Notes on the Time-base Timer ............................................................................................ 214
10.7
Sample Program for the Time-base Timer Program ....................................................................... 216
CHAPTER 11 WATCHDOG TIMER ................................................................................ 219
11.1
Overview of the Watchdog Timer ................................................................................................... 220
11.2
Configuration of the Watchdog Timer ............................................................................................. 221
11.3
Watchdog Timer Control Register (WDTC) .................................................................................... 222
11.4
Operation of the Watchdog Timer ................................................................................................... 224
11.5
Usage Notes on the Watchdog Timer ............................................................................................. 226
11.6
Sample Program for the Watchdog Timer ...................................................................................... 227
vii

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