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Table 15.4-2 Output Control Lower Register (OPCLR) Bits
Bit name
PDIF:
Position detect
bit7
interrupt flag
bit
PDIE:
Position detect
bit6
interrupt enable
bit
OPE5 to OPE0:
bit5
OPT5 to OPE0
to
output enable
bit0
bits
• Position detection interrupt request flag.
• It is an interrupt request flag for the position detection. When CMPE is set to "0" and the
SNI2 to SNI0 bits are compared and matched with the RDA2 to RDA0 bit, or when CMPE
is set to "1" and any effective edge is detected at SNI2 to SNI0 pins, this bit is set to "1".
• When this bit is set to "1", the interrupt is generated if the position detection interrupt
enable bit (PDIE) is also set to "1". This bit is cleared by writing "0". Writing "1" has no
effect.
• In read-modify-write operation, "1" is always read.
• Position detection interrupt enable bit.
• When this bit is set to "1", the interrupt is generated if position detection interrupt request
flag (PDIF) is also set to "1".
• Output enable bits of OPT5 to OPE0 pins.
• When these bits are set, the outputs to the OPT5 to OPE0 pins are enable.
CHAPTER 15 MULTI-PULSE GENERATOR
Function
375
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