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CHAPTER 23 512K / 1024K BIT FLASH MEMORY
23.3
Flash Memory Control Status Register (FMCS)
The FMCS, which exists in the flash memory interface circuit, is used when data is
written to or erased from flash memory.
■ Control Status Register (FMCS)
bit
Address:0000AE
H
Read/Write
Initial value
●
Contents of the bits
[bit7] INTE (Interrupt Enable)
This bit generates an interrupt to the CPU when the write/delete operation to the flash memory is
terminated.
When the INTE bit is "1" and the RDYINT bit is "1" an interrupt generated and sent to the CPU. If the
INTE bit is "0", no interrupt is generated:
0: Interrupt disabled when the write/delete operation is terminated.
1: Interrupt enabled when the write/delete operation is terminated.
[bit6] RDYINT (Ready Interrupt)
This bit indicates the flash memory operating status.
After the write/delete to the flash memory is terminated, this bit is set to "1". While this bit is "0" after
the end of write/delete operation to the flash memory, the flash memory cannot be written or deleted.
After the write/delete operation is terminated and this bit is set to "1", the flash memory can be written
or deleted. This bit is cleared to "0" by writing "0" and the writing of "1" is ignored. At the termination
time of the automatic algorithm in the flash memory (see "23.4 Method of Starting the Automatic
Algorithm in Flash Memory"), this bit is set to "1". While using the read modify write (RMW)
instruction, "1" can be read at any time.
0: During the write/delete operation
1: Write/delete operation terminated (An interrupt request is generated)
[bit5] WE (Write Enable)
This bit is the write enable bit for the flash memory area.
When this bit is "1", the write instruction after issuing command sequence to FF bank (see "23.4
Method of Starting the Automatic Algorithm in Flash Memory") is equivalent to writing to the flash
memory area. When this bit is "0", no write/delete signal is generated. This bit is used when the flash
memory write/delete command is started.
0: Flash memory write/delete disabled
1: Flash memory write/delete enabled
590
7
6
WE
INTE
RDYINT
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
5
4
3
RDY
Reserved
(R)
(W)
(1)
(0)
2
1
LPM1
Reserved
(W)
(W)
(0)
(0)
0
LPM0
(R/W)
(0)
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