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CHAPTER 7 INTERRUPT
Table 7.3-2 Correspondence between the Interrupt Level Setting Bits and Interrupt Levels
IL2
0
0
0
0
1
1
1
1
●
Extended intelligent I/O service (EI
If this bit is "1" when an interrupt request is generated, EI
interrupt request is generated, the interrupt sequence is activated. When the EI
met (when the S1 and S0 bits are not 00
does not have the EI
"0" by a reset.
●
Extended intelligent I/O service (EI
These write-only bits specify the EI
value set here. The ICS bit is initialized to 0000
Table 7.3-3 shows the correspondence between the EI
Table 7.3-3 Correspondence between the EI
ICS3
0
0
0
0
0
0
0
0
124
IL1
IL0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
2
OS) enable bit (ISE)
2
OS function, the ISE bit must be set to "0" by software. The ISE bit is initialized to
2
OS) channel selection bits (ICS3 to ICS0)
2
OS channel. The EI
Addresses (1 / 2)
ICS2
ICS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
2
OS is activated. If this bit is "0" at when an
), the ISE bit is cleared. If the corresponding peripheral function
B
2
OS descriptor address is determined based on the
by a reset.
B
2
OS channel selection bits and descriptor addresses.
2
OS Channel Selection Bits and Eescriptor
ICS0
Selected channel
0
0
1
1
0
2
1
3
0
4
1
5
0
6
1
7
Interrupt level
0 (highest priority)
6 (lowest priority)
7 (no interrupt)
2
OS termination condition is
Descriptor address
000100
000108
000110
000118
000120
000128
000130
000138
H
H
H
H
H
H
H
H
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