Pwc Timer Interrupts - Fujitsu MB90460 Series Hardware Manual

16.5

PWC Timer Interrupts

The PWC timer is enabled to generate an interrupt request in an overflow of the counter
or measurement terminated in pulse-width measurement mode. It is also coordinated
with the extended intelligent I/O service (EI
■ PWC Timer Interrupts
Table 16.5-1 lists the interrupt control bits and interrupt causes of the PWC timer.
Table 16.5-1 Interrupt Control Bits and Interrupt Causes of the PWC Time
Interrupt request flag bit
Interrupt request enable bit PWCSL0: OVIE
Interrupt cause
In the PWC timer, the OVIR bit of the PWC control status register (PWCSL) is set to "1" by an overflow
(from FFFF
operation, the interrupt request is output to the interrupt controller.
The EDIR bit of the PWC control status register (PWCSL) is set to "1" by measurement terminated in
pulse-width measurement mode. If an interrupt request is enabled (PWCSL:EDIE = 1) in this operation,
the interrupt request is output to the interrupt controller.
■ PWC Timer Interrupts and EI
Table 16.5-2 lists the PWC timer interrupts and EI
Table 16.5-2 16-bit PWC Timer Interrupts and EI
Interrupt
Channel
number
*1
#13 (0D
PWC timer 0
*2
#24 (18
PWC timer 1
*1: The same interrupt number as that for 16-bit PPG timer 0 is assigned to PWC timer 0.
*2: The same interrupt number as that for output compare channel 5 match is assigned to PWC timer 1.
PWC timer 0
PWCSL0: OVIR PWCSL0: EDIR
PWCSL0: EDIE
Measurement
Overflow of the 16-bit terminated in pulse-
up counter width measurement
mode
to 0000 ) of the up counter. If an interrupt request is enabled (PWCSL:OVIE = 1) in this
H H
2
OS
Interrupt control register
Register
Address
name
) 0000B1
ICR01
H
) 0000B6
ICR06
H
2
OS).
PWCSL1: OVIR
PWCSL1: OVIE
Overflow of the 16-bit
up counter
2
OS.
2
OS
Vector table address
Lower
FFFFC8
H H
FFFF9C
H H
CHAPTER 16 PWC Timer
PWC timer 1
PWCSL1: EDIR
PWCSL1: EDIE
Measurement
terminated in pulse-
width measurement
mode
Middle Upper
FFFFC9 FFFFCA
H H
FFFF9D FFFF9E
H H
2
EI OS
O
445