Block Diagram Of The 16-Bit Reload Timer - Fujitsu MB90460 Series Hardware Manual

12.2

Block Diagram of the 16-bit Reload Timer

There are two 16-bit reload timers in MB90460/465 series. Each of them consists of the
seven blocks as shown in the block diagram below.
■ Block Diagram of the 16-bit Reload Timer
Figure 12.2-1 shows the block diagram of the 16-bit reload timer
Count clock generation
circuit
Machine
clock
P15
P20
*1 This register includes channel 0 and channel 1. The register enclosed in < and > indicates the
channel 1 register.
*2 Interrupt number
●
Count clock generation circuit
This circuit generates the count clock for the 16-bit reload timer from the machine clock or external input
clock.
●
Reload control circuit
This circuit controls the reload operation when the timer is started and when an underflow occurs.
Figure 12.2-1 Block Diagram of the 16-bit Reload Timer
F
TMRD0*1
<TMRD1>
16-bit reload register
16-bit timer register
Gate
input
Pre-
scaler
Clear
Internal
clock
Input
Pin control
circuit
External clock
Function selection
Timer control status register (TMCSR0)(*1) <TMCSR1>
2
MC-16LX bus
Reload signal
Valid
Wait signal
clock
judgment
circuit
Output control circuit
Output signal
Clock
generation
Invert circuit
selector
Select
signal
CHAPTER 12 16-BIT RELOAD TIMER
Reload
control circuit
To UART0 and
UART1 (*1)
<To the A/D
converter>
Pin
P16/TO0(*1)
<P21/TO1>
Operation
control
circuit
Interrupt request signal
#30 (1EH)(*2)
<#18 (12H)>
233