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17.5.2
Transmission Interrupt Generation and Flag Set Timing
A transmission interrupt is generated when the next piece of data is ready to be written
to the output data register (SODR0/SODR1).
■ Transmission Interrupt Heneration and Flag Set Timing
The transmission data empty flag bit (SSR0/SSR1: TDRE) is set to "1" when data written to the output data
register (SODR0/SODR1) is transferred to the transmission shift register, and the next piece of data is
ready to be written. TDRE is cleared to "0" when transmission data is written to SODR0/SODR1. Figure
17.5-2 shows the transmission operation and flag set timing.
[Operation modes 0 and 1]
SODR write
TDRE
SOT interrupt
SOT output
[Operation mode 2]
SODR write
TDRE
SOT interrupt
SOT output
ST: Start bit
D0 to D7: Data bits
●
Transmission interrupt request generation timing
If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR0/SSR1: TIE = 1), transmission
interrupt requests (#38 and #40) are generated.
Note:
A transmission completion interrupt is generated immediately after the transmission interrupts are
enabled (TIE = 1) because the TDRE bit is set to "1" as its initial value. TDRE is a read-only bit that
can be cleared only by writing new data to the output data register (SODR0/SODR1). Carefully
specify the transmission interrupt enable timing.
Figure 17.5-2 Transmission Operation and Flag Set Timing
An interrupt request is issued to the CPU.
ST D0 D1 D2 D3 D4 D5 D6 D7 SP
An interrupt request is issued to the CPU.
D0
D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3
SP: Stop bit
SP ST D0 D1 D2 D3
A/D
A/D: Address/data multiplexer
CHAPTER 17 UART
D4 D5 D6 D7
489
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