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Table 17.1-2 UART Operation Mode
Operation mode
0
Normal mode
1
Multiprocessor
2
Normal mode
– : Setting not possible.
*1: "+1" indicates the address/data selection bit (A/D) for communication control.
*2: During reception, only one stop bit can be detected.
■ UART Interrupt and EI
Table 17.1-3 UART Interrupt and EI
Interrupt cause
UART1 reception
interrupt
UART1 transmission
interrupt
UART0 reception
interrupt
UART0 transmission
interrupt
: Provided with a function that detects a UART reception error and stops EI
∆ : Usable when ICR13 and ICR14 or interrupt causes that share an interrupt vector are not used
When parity is
disabled
1
8+1*
bits
8 bits
2
OS
2
OS
Interrupt control register
Interrupt
number
Register
name
#37(25
)
ICR13
H
#38(26
)
ICR13
H
#39(27
)
ICR14
H
#40(28
)
ICR14
H
Data length
When parity is
enabled
7 or 8 bits
–
–
Vector table address
Address
Lower
0000BD
FFFF68
H
H
0000BD
FFFF64
H
H
0000BE
FFFF60
H
H
0000BE
FFFF5C
H
H
2
OS
CHAPTER 17 UART
Synchronization
Stop bit length
on mode
Asynchronous
1 or 2 bits *
Asynchronous
Synchronous
Upper
Bank
FFFF69
FFFF6A
H
H
FFFF65
FFFF66
H
H
FFFF61
FFFF62
H
H
FFFF5D
FFFF5E
H
H
2
None
EI²OS
∆
∆
469
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